EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 393

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

MaxFrmLen
DS785UM1
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
RSVD
RSVD
29
13
28
12
TDST:
0x8001_00E8 - Read/Write
0x0000_0000
Unchanged
Maximum Frame Length and Transmit Start Threshold register.
RSVD:
MFL:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Transmit Descriptor Soft Threshold.
The hard and soft threshold work in exactly the same
manner except one. The soft threshold will not cause a
bus request to be made if the bus is currently in use, but
only when it is deemed to be idle (no transfers for four
AHB clocks). The hard threshold takes effect immediately
regardless of the state of the bus. This operation allows for
more efficient use of the AHB bus by allowing smaller
transfers to take place when the bus is lightly loaded and
requesting larger transfers only when the bus is more
heavily loaded.
Reserved. Unknown During Read.
Maximum Frame Length. The maximum frame length is a
limit for the amount of data permitted to be transferred
across the AHB bus for a transmit frame, or on the wire for
a receive frame. When this limit is reached for a transmit
frame, the Transmit Descriptor Processor is halted and a
transmit length error is set in the Interrupt Status register.
When the limit is reached for a receive frame, no further
data will be transferred to memory for the current frame.
The status written for the frame will indicate the length
error, and further frames will continue as normal, (the
Receive Descriptor Processor will not halt).
24
8
23
7
22
6
MFL
TST
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
9-91
0
9