EP9312-CB Cirrus Logic Inc, EP9312-CB Datasheet - Page 433

• Manufacturer Part Number: EP9312-CB
• Description: System-on-Chip Processor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-CB

• Peak Reflow Compatible (260 C): No
• A/d Converter: 12 Bits
• Leaded Process Compatible: No
• No. Of I/o Pins: 65
• Package / Case: 352-BGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1257

DS785UM1
EOTS:
NFB:
NB:
Copyright 2007 Cirrus Logic
End-Of-Transfer status (valid only if the DEOT/TC pin has
been programmed for the DEOT function, that is, the
control reg bit ETDP[1] = 0) for buffer descriptor 1 or 0
respectively.
00 - End of transfer has not been requested by external
device for either buffer descriptor.
01 - End of transfer has been requested by external device
for buffer descriptor 0 only.
10 - End of transfer has been requested by external device
for buffer descriptor 1 only.
11 - End of transfer has been requested by external
peripheral for both buffer descriptors.
A “1” indicates that the channel is currently transferring
data from a DMA buffer but the next byte count register for
the next buffer in the transfer has not been programmed,
and may now be programmed. This interrupt is generated
when the DMA buffer state machine moves from the
DMA_BUF_NEXT state to the DMA_BUF_ON state, that
is, when transfer begins using the second buffer of the
double buffer pair. Thus for a double-buffer transfer both
BCR registers must be programmed once before the NFB
status bit can be used to determine when the next BCR
register should be programmed.
0 - Not ready for next buffer update.
1 - Ready for next buffer updates. NFB interrupt generated
if not masked.
NextBuffer status bit - Informs the NFB service routine,
after a NFB interrupt, which pair of
SAR_BASEx/DAR_BASEx/BCRx registers is free for
update.
0 - Update SAR_BASE0/DAR_BASE0/BCR0
1 - Update SAR_BASE1/DAR_BASE1/BCR1
The NextBuffer bit gets set to “1” when a write occurs to
BCR0 and it gets set to “0” when a write occurs to BCR1.
This bit alone cannot be used to determine which of the
two buffers is currently being transferred to - for example if
BCR0 is written, then NextBuffer gets set to “1” and
transfers will occur using buffer0. If, during this transfer
BCR1 gets written, then NextBuffer gets set to “0”, but the
current transfer will continue using buffer0 until it
terminates. Then the DMA switches over to using buffer1
at which time the NFB interrupt is generated and software
reads the NextBuffer status bit to determine what buffer
descriptor is now free for update - in this case it is buffer0.
EP93xx User’s Guide
DMA Controller
10-39
10