IP-CPRI Altera, IP-CPRI Datasheet - Page 122

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–20
Table 6–50. ETH_TX_STATUS—Ethernet Transmitter Module Status—Offset: 0x204
Table 6–51. ETH_CONFIG_1—Ethernet Feature Configuration 1—Offset: 0x208
CPRI MegaCore Function User Guide
RSRV
tx_ready_block
rx_abort
rx_ready
RSRV
intr_tx_ready_block_en
intr_tx_abort_en
intr_tx_ready_en
intr_rx_ready_block_en
intr_rx_ready_end_en
intr_rx_abort_en
intr_rx_ready_en
intr_tx_en
intr_rx_en
intr_en
rx_long_frame_en
rx_preamble_abort_en
broadcast_en
multicast_flt_en
mac_check
length_check
RSRV
little_endian
RSRV
Field
Field
[31:3] UR0
[2]
[1]
[0]
Bits
Access
RO
RO
RO
[31:20] UR0
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3:2]
[1]
[0]
Bits
Reserved.
Indicates that the Ethernet Tx module is ready to receive an 8-word
block of data from the Ethernet channel.
Indicates the current Ethernet Tx packet is aborted.
Indicates that the Ethernet Tx module is ready to receive at least one
32-bit word of data from the Ethernet channel.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RO
Reserved.
Indicates an interrupt is generated when
tx_ready_block is asserted, if intr_en and
intr_tx_en are asserted.
Indicates an interrupt is generated when tx_abort is
asserted, if intr_en and intr_tx_en are asserted.
Indicates an interrupt is generated when tx_ready is
asserted, if intr_en and intr_tx_en are asserted.
Indicates an interrupt is generated when
rx_ready_block is asserted, if intr_en and
intr_rx_en are asserted.
Indicates an interrupt is generated when rx_ready_end is
asserted, if intr_en and intr_rx_en are asserted.
Indicates an interrupt is generated when rx_abort is
asserted, if intr_en and intr_rx_en are asserted.
Indicates an interrupt is generated when rx_ready is
asserted, if intr_en and intr_rx_en are asserted.
Ethernet Tx interrupt enable.
Ethernet Rx interrupt enable.
Ethernet global interrupt enable.
Enable reception of Rx Ethernet frames longer than 1536
bytes.
Indicates that Rx frames with an illegal preamble nibble
before the SFD are discarded.
Enable reception of Ethernet broadcast packets.
Enable reception of multicast Ethernet packets allowed by
the hash function.
Enable check of Rx Ethernet MAC address.
Indicates that a length check is performed on Rx packets,
and those with length less than 64 bytes are discarded.
Reserved.
Indicates that the Ethernet channel receive and transmit
data is formatted in little endian byte order.
Reserved.
Function
Function
Chapter 6: Software Interface
May 2011 Altera Corporation
Ethernet Registers
29'h0
1’h0
1’h0
1’h0
Default
11'h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
1’h0
2’h0
1’h0
1'h0
Default