IP-CPRI Altera, IP-CPRI Datasheet - Page 69

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
Figure 4–22. Tx Path Delay from AUX Interface or Through CPRI Map Interface Block to CPRI Link
May 2011 Altera Corporation
tx_dataout
Tx Path Delay
Transceiver
Transmitter
4. Consult
5. Calculate the full Rx path delay to the AUX interface by adding the values you
The Tx path delay is the cumulative delay from the arrival of the first bit of a 10 ms
radio frame on the CPRI AUX interface to the start of transmission of this data on the
CPRI link. This section provides the information to calculate the Tx path delay.
However, the delay through the MAP interface module to the CPRI link is the same as
the delay from the AUX interface.
paths.
In the CPRI IP core the delay from the AUX interface is fixed. This path has no
variable delay component, because it does not cross clock domains.
The Tx path delay from the AUX interface comprises the following delays:
1. Fixed delay from the AUX interface through the CPRI low-level transmitter to the
2. Link delay through the transceiver. This delay is T_txv_TX in
(2)
the AUX interface. For the example, the duration of this delay is 6.75 cpri_clkout
clock cycles.
derived in step
delay as follows:
Rx path delay = T_txv_RX + <delay through Rx Receive buffer>
The best case Rx path delay has zero byte alignment delay, for a total delay of
44.636 cpri_clkout clock cycles.
transceiver. This delay depends on the device family and CPRI data rate. This
delay is T_T4 in
“Fixed Tx Core Delay Component” on page
page
4–46.
Physical Layer
Transmitter
Table 4–8 on page 4–44
= 4.65 + 33.236 + 1 + 6.75 cpri_clkout clock cycles
= 45.636 cpri_clkout clock cycles
1
Figure 4–19 on page 4–39
through step 4. For the example, calculate the worst case Rx path
AUX Interface
(1)
(1)
+ <worst case variable byte alignment delay>
+ <delay to AUX IF>
Module
AUX
Figure 4–22
to determine the delay through the CPRI IP core to
Interface Module
CPRI MAP
and in
shows the relation between the two Tx
4–46.
Table 4–9 on page
AxC IF 0
AxC IF n
CPRI MegaCore Function User Guide
Table 4–10 on
Data Channels
4–46. Refer to
4–45