IP-CPRI Altera, IP-CPRI Datasheet - Page 61

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Auxiliary Interfaces
Figure 4–17. AUX Interface Outgoing Data at Different CPRI Line Rates (Part 3 of 3)
6144.0 Mbps
Line Rate:
Note to
(1) Light blue table cells indicate control word bytes. White table cells indicate data word bytes.
May 2011 Altera Corporation
Figure
[31:24]:
[23:16]:
AUX Transmitter Module
[15:8]:
[7:0]:
4–17:
#Z.X.0.0
#Z.X.0.1
#Z.X.0.2
#Z.X.0.3
The AUX transmitter module receives data on the incoming AUX Avalon-ST interface
and sends it to the CPRI IP core to transmit on the CPRI link. In addition, it outputs
CPRI link frame synchronization information, to enable synchronization of the AUX
data.
The incoming data on the AUX interface must match the output frame
synchronization information with a delay of exactly two cpri_clkout clock cycles.
Figure 4–18
Figure 4–18. Incoming AUX Link Synchronization
Note to
(1) The cpri_tx_aux_data and cpri_tx_aux_mask signals are fields in the aux_tx_mask_data input bus. Refer to
The AUX transmitter module also receives a synchronization pulse that overrides the
current state of the frame synchronization machine. REC master IP cores use the
cpri_tx_sync_rfp input signal to control the start of a new 10 ms radio frame.
Application software can assert this signal as a pulse less than 10 ms after the rising
edge of the previous cpri_tx_rfp output pulse to resynchronize the frame sequence.
Asserting this signal resets the frame synchronization machine in the REC master.
The AUX interface transmitter module derives frame synchronization information
from the CPRI transmitter frame synchronization state machine. It provides the
cpri_tx_aux_mask
cpri_tx_aux_data
0
Table 5–13 on page
(1)
(1)
(1)
(1)
cpri_tx_seq
Figure
4–18:
shows the expected timing on the incoming AUX connection.
#Z.X.0.4
#Z.X.0.5
#Z.X.0.6
#Z.X.0.7
(1)
(1)
1
5–12.
2 cpri_clkout cycles
(1)
(1)
(1)
(1)
0
Sequence number on AUX interface
#Z.X.0.8
#Z.X.0.9
1
#Z.X.1.0
#Z.X.1.1
2
(1)
(1)
Basic Radio Frame
2
0
1
...
...
...
...
...
2
num_seq-1
#Z.X.15.2
#Z.X.15.3
#Z.X.15.4
#Z.X.15.5
CPRI MegaCore Function User Guide
38
2 cpri_clkout cycles
#Z.X.15.6
#Z.X.15.7
#Z.X.15.8
#Z.X.15.9
num_seq-1
39
4–37