IP-CPRI Altera, IP-CPRI Datasheet - Page 65

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
Figure 4–21. Rx Path Delay to AUX Output and Through CPRI Map Interface Block
May 2011 Altera Corporation
rx_datain
Transceiver
Receiver
(1a)
Rx Path Delay Components
The CPRI specification defines requirements on the path to an SAP. The CPRI IP core
has one relevant SAP, the AUX interface. This section provides the information to
calculate the Rx path delay to output on the AUX interface.
However, the delay to—but not through—the AxC blocks, that is, the delay through
the MAP interface module, is the same as the delay to the AUX interface.
shows the relation between the two Rx paths.
The Rx path delay to the AUX interface or through the CPRI MAP interface module is
the sum of the following delays:
1. The link delay is the delay between the arrival of the first bit of a 10 ms radio
2. Delay from the CPRI low-level receiver block to the AUX interface (or through the
The following sections describe the individual delays and how to calculate them.
frame on the CPRI Rx interface and the CPRI IP core internal transmission of the
radio frame pulse from the CPRI interface Rx module. The link delay includes the
following delays:
a. Transceiver latency is a fixed delay through the deterministic latency path of
b. Delay through the clock synchronization FIFO, as well as the phase difference
c. Byte alignment delay that can occur as data is shifted out of the Rx elastic
CPRI MAP interface block). This delay depends on the device family and CPRI
data rate. This delay is T_R1 in
Delay Component” on page
Receiver
the transceiver. Its duration depends on the device family and on the path
direction (Rx or Tx). This delay includes comma alignment. Refer to
Transceiver Latency”
between the recovered receive clock and the core RE clock cpri_clkout. The
“Extended Rx Delay Measurement”
in the CPRI Rx elastic buffer, which includes the phase alignment delay.
buffer. This variable delay appears in the rx_byte_delay field of the
CPRI_RX_DELAY register — when the value in rx_byte_delay is non-zero, a byte
alignment delay of one cpri_clkout cycle occurs in the Rx path.
Physical Layer
Rx Elastic
Buffer
(1b)
(1c)
AUX Interface
(2)
on the following pages.
(2)
Module
AUX
4–44.
Figure 4–19 on page
Interface Module
CPRI MAP
section shows how to calculate the delay
AxC IF 0
AxC IF n
4–39. Refer to
CPRI MegaCore Function User Guide
Data Channels
“Fixed Rx Core
Figure 4–21
“Rx
4–41