IP-CPRI Altera, IP-CPRI Datasheet - Page 73

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Delay Measurement
May 2011 Altera Corporation
9. Calculate
10. Perform the final calculation. Calculate
This example shows the calculation for the case of two link partner CPRI IP cores
configured with autorate negotiation enabled on Arria II GX devices, in a single-hop
configuration, running at CPRI data rate 3.072 Gbps.
The calculation is identical to the calculation in Example 1, except that the fixed and
transceiver delays are different in Arria II GX devices than in Stratix IV GX devices. In
addition, Example 2 has a different value in the rx_round_trip_delay register field. In
your own system, the Rx elastic buffer delay and byte-alignment delays may also
vary.
To calculate the round-trip cable delay in this system, follow these steps:
1. Read the value in the rx_round_trip_delay field of the CPRI_ROUND_DELAY register
2. For each of the REC master and the RE slave, read the value in the
3. For each of the REC master and the RE slave, divide the value in the
4. Calculate the Rx path delay through the RE slave, by following the steps in
Toffset = <RE Rx path delay> + <RE Tx path delay> + <loopback delay>,
Round-trip cable delay = T14 – Toffset
(at register offset 0x38) of the REC master. For the example, the value is 0x57,
which is decimal 87.
rx_ex_buf_delay field of the CPRI_EX_DELAY_STATUS register (at register offset
0x40) and the value in the rx_ex_delay field of the CPRI_EX_DELAY_CONFIG register.
Read the rx_ex_buf_delay field only after the rx_ex_buf_delay_valid bit in the
register is high.
rx_ex_buf_delay register field by the value in the rx_ex_delay register field. The
result is the current Rx elastic buffer delay in cpri_clkout cycles. In this example,
the Rx elastic buffer delay in the REC master is 32.25 cpri_clkout cycles, and the
Rx elastic buffer delay in the RE slave is 8.9 cpri_clkout cycles.
Path Delay to AUX Output: Calculation Example” on page
the value in the rx_byte_delay field of the CPRI_RX_DELAY register of the RE slave
is zero, so the byte-alignment delay is zero. According to
the correct value of T_txv_RX is 4.65 cpri_clkout cycles. According to
on page
delay is 8.9 cpri_clkout cycles, yielding a total delay of 20.3 cpri_clkout cycles.
20.3 = <fixed transceiver delay> + <fixed core delay> + <Rx buffer delay> +
Round-Trip and Cable Delay Calculation Example 2: Two Arria II GX Devices
= 4.65 + 6.75 + 8.9 + 0
= 19.4 + 9.5 + 1
= 29.9 cpri_clkout cycles
4–44, the correct value of T_R1 is 6.75 cpri_clkout cycles. The Rx buffer
<byte-alignment delay>
= 31.75 – 29.9
= 1.85 cpri_clkout cycles
CPRI MegaCore Function User Guide
Table 4–6 on page
4–44. In this example,
Table 4–8
“Rx
4–42,
4–49