IP-CPRI Altera, IP-CPRI Datasheet - Page 143

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Appendix B: Implementing CPRI Link Autorate Negotiation
Configuring the CPRI IP Core for Autorate Negotiation
Figure B–2. Autorate Negotiation in Master Clocking Mode
Notes for
(1) Optional clock switching logic determines the value of gxb_refclk, depending on the desired transceiver frequency setting.
(2) The number of ROMs and the rate requirements are design dependent.
Configuring the CPRI IP Core for Autorate Negotiation
Running Autorate Negotiation
May 2011 Altera Corporation
Figure
(2)
frame synchronization
line rate based on
Software controls
FSM feedback.
B–2:
614.4 Mbps
MIF file in
1228.8 Mbps
MIF file in
2457.6 Mbps
MIF file in
6144.0 Mbps
MIF file in
3072.0 Mbps
MIF file in
4915.2 Mbps
MIF file in
ROM
ROM
ROM
ROM
ROM
ROM
To ensure that the CPRI IP core implements autorate negotiation correctly, while
configuring your CPRI IP core, enable autorate negotiation and set the CPRI line rate
to the maximum line rate supported by the device family.
After your CPRI IP core is configured on the device, the autorate negotiation logic you
configured in your design outside the CPRI IP core must perform certain steps to
activate the autorate negotiation support logic in the CPRI IP core. This section
describes these steps.
To start autorate negotiation in your CPRI IP core, in addition to its own initialization
outside the CPRI IP core, your hardware and software must perform the following
steps:
1. Confirm that the i_datarate_en bit of the AUTO_RATE_CONFIG register is set to 1.
(2)
The AUTO_RATE_CONFIG register is described in
read this value on the datarate_en output signal.
614.4 Mbps
MIF file in
1228.8 Mbps
MIF file in
3072.0 Mbps
MIF file in
2457.6 Mbps
MIF file in
ROM
ROM
ROM
ROM
Line Rate
GPLL
(1)
122.88 MHz
15.36 MHz
30.72 MHz
61.44 MHz
153.6 MHz
76.8 MHz
ALTPLL_RECONFIG
ALTGX_RECONFIG
(for Cyclone IV GX
devices)
gxb_refclk
Table 6–21 on page
AUTORATE_CONFIG
Register
CPRI MegaCore Function
pll_inclk
reconfig_fromgxb
reconfig_togxb
To MPLL
in Cyclone IV GX
devices
CPRI MegaCore Function User Guide
datarate_en
datarate_set
ALTGX
6–10. You can
B–3