IP-CPRI Altera, IP-CPRI Datasheet - Page 88
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IP-CPRI
Manufacturer Part Number
IP-CPRI
Description
IP CORE - Common Public Radio Interface (CPRI)
Manufacturer
Altera
Specifications of IP-CPRI
Software Application
IP CORE, Interface And Protocols, HIGH SPEED
Supported Families
Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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5–2
Table 5–4. Autorate Negotiation Signals
Table 5–5. Scan-Chain Based Reconfiguration Interface Signals For CPRI Autorate Negotiation in Cyclone IV GX Devices
CPRI MegaCore Function User Guide
datarate_en
datarate_set
pll_areset
pll_configupdate
pll_scanclk
pll_scanclkena
pll_scandata
pll_reconfig_done
pll_scandataout
Signal
Autorate Negotiation Signals
Signal
Output
Output
Direction
Table 5–4
signals enable the autorate negotiation hardware and software outside the CPRI IP
core to quickly monitor autorate negotiation status, and are implemented in all device
families.
In Cyclone IV GX devices, channel reconfiguration is enabled to support autorate
negotiation.
Cyclone IV GX devices to support scan-chain based reconfiguration.
Input
Input
Input
Input
Input
Output
Output
Direction
Indicates whether autorate negotiation is enabled. This signal reflects the value in the
i_datarate_en field of the AUTO_RATE_CONFIG register described in
page
CPRI line rate to be used in next attempt to achieve frame synchronization. This signal
reflects the value currently in the i_datarate_set field of the AUTO_RATE_CONFIG
register described in
The CPRI line rate is encoded in this field with the following values:
lists the autorate negotiation signals for the CPRI IP core. These output
0001: 614.4 Mbps
0010: 1228.8 Mbps
0100: 2457.6 Mbps
0101: 3072.0 Mbps
1000: 4915.0 Mbps (not supported for Cyclone IV GX devices)
1010: 6144.0 Mbps (not supported for Cyclone IV GX devices)
Table 5–5
6–10.
Resets the PLL. Signal must be asserted after PLL reconfiguration. Connect to the
areset signal for the PLL.
When this signal is asserted, the PLL counters are updated with the contents of the
scan chain. Signal is asserted for a single pll_scanclk cycle. Connect to the PLL
reconfiguration scan chain configupdate signal.
Clocks the shift registers in the PLL reconfiguration scan chain.The maximum
frequency of this clock is 100 MHz.
Indicates scan data can be shifted in on the following pll_scanclk cycle. Connect
to the PLL reconfiguration scan chain scanclkena signal.
Serial data scanned into the scan chain. Connect to the PLL reconfiguration scan
chain scandata signal.
Indicates PLL reconfiguration is complete.
Output stream shifted out of the scan chain.
lists the signals implemented in CPRI IP cores targeted to
Table 6–21 on page
Description
6–10.
Description
May 2011 Altera Corporation
Table 6–21 on
Physical Layer Signals
Chapter 5: Signals
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