IP-CPRI Altera, IP-CPRI Datasheet - Page 66

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–42
CPRI MegaCore Function User Guide
Rx Transceiver Latency
The Altera high-speed transceiver is implemented using the deterministic latency
protocol, which ensures that delays in comma alignment and in byte alignment within
the transceiver are consistent.
Table 4–6
CPRI IP core. These values correspond to T_txv_RX in
Table 4–6. Fixed Latency T_txv_RX Through Receiver Transceiver
The clean-up PLL shown in
Figure 4–6 on page 4–11
the gxb_pll_inclk signal, to ensure frequency match. To preserve the T_txv_RX
latency in
contains no asynchronous dividers.
Extended Rx Delay Measurement
The second component of the link delay is the delay through the CPRI Receive buffer.
The latency of the CPRI Receive buffer depends on the number of 32-bit words
currently stored in the buffer, and the phase difference between the recovered receive
clock, which is used to write data to the buffer, and the system clock cpri_clkout,
which is used to read data from the buffer. The CPRI IP core uses a dedicated clock,
clk_ex_delay, to measure the Rx buffer delay to your desired precision. The
rx_ex_delay field of the CPRI_EX_DELAY_CONFIG register contains the value N, such
that N clock periods of the clk_ex_delay clock are equal to some whole number M of
cpri_clkout periods. For example, N may be a multiple of M, or the M/N frequency
ratio may be slightly greater than 1, such as 64/63 or 128/127. The application layer
specifies N to ensure the accuracy your application requires. The accuracy of the Rx
buffer delay measurement is N/least_common_multiple(N,M) cpri_clkout periods.
The rx_buf_delay field of the CPRI_RX_DELAY register indicates the number of 32-bit
words currently in the Rx buffer. After you program the rx_ex_delay field of the
CPRI_EX_DELAY_CONFIG register with the value of N, the rx_ex_buf_delay field of the
CPRI_EX_DELAY_STATUS register holds the current measured delay through the Rx
buffer. The unit of measurement is cpri_clkout periods. The rx_ex_buf_delay_valid
field indicates that a new measurement has been written to the rx_ex_buf_delay field
since the previous register read. The following sections explain how you set and use
these register values to derive the extended Rx delay measurement information.
Arria II GX or Cyclone IV GX Device
shows the fixed latency through the transceiver in the receive side of the
Table
4–6, you must ensure that the reference clock to the clean-up PLL
Latency Through Transceiver in cpri_clkout Clock Cycles
4.65
uses the recovered clock as input to the PLL that generates
Figure 4–2 on page
4–7,
Arria II GZ or Stratix IV GX Device
Figure 4–4 on page
Figure
Chapter 4: Functional Description
4–19.
6.5
May 2011 Altera Corporation
Delay Measurement
4–9, and