IP-CPRI Altera, IP-CPRI Datasheet - Page 92

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–6
Table 5–7. CPU Interface Signals (Part 2 of 2)
CPRI MII Interface Signals
Table 5–8. CPRI MII Receiver Interface Signals
CPRI MegaCore Function User Guide
cpu_readdata[31:0]
cpu_waitrequest
cpri_mii_rxclk
cpri_mii_rxwr
cpri_mii_rxdv
cpri_mii_rxer
cpri_mii_rxd[3:0]
CPRI MII Interface Receiver Signals
Signal
Signal
Table 5–8
CPRI IP core. The CPRI MII interface is enabled if you turn off Include MAC block in
the CPRI parameter editor. The CPRI MII interface signals are available only if you
enable the CPRI MII interface. For information about the MII handshaking protocol
implementation, refer to
Table 5–8
Output
Output
Output
Output
Output
Direction
Output
Output
Direction
and
lists the CPRI MII interface receiver signals.
Table 5–9
Clocks the MII receiver interface. The cpri_clkout clock drives this signal.
Ethernet write signal. Indicates the presence of a new K nibble or data value on
cpri_mii_rxd[3:0]. This signal is asserted during the first cpri_mii_rxclk
cycle in which the K nibble or a new data value appears on cpri_mii_rxd[3:0].
Ethernet receive data valid. Indicates the presence of valid data or initial K nibble on
cpri_mii_rxd[3:0].
Ethernet receive error. Indicates that the CPRI link is not initialized, and therefore
an error might be present in the frame being transferred to the external Ethernet
block. This signal is deasserted at reset, and asserted after reset until the CPRI IP
core achieves frame synchronization.
Ethernet receive nibble data. Data bus for data from the CPRI IP core to the
external Ethernet block. All bits are deasserted during reset, and all bits are
asserted after reset until the CPRI IP core achieves frame synchronization.
CPU read data.
Indicates that the CPU interface is busy executing an operation. When this
signal is deasserted, the operation is complete and the data is valid.
list the signals used by the CPRI MII interface module of the
“MII Interface” on page
Description
Description
4–4.
May 2011 Altera Corporation
CPRI MII Interface Signals
Chapter 5: Signals