IP-CPRI Altera, IP-CPRI Datasheet - Page 29
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IP-CPRI
Manufacturer Part Number
IP-CPRI
Description
IP CORE - Common Public Radio Interface (CPRI)
Manufacturer
Altera
Specifications of IP-CPRI
Software Application
IP CORE, Interface And Protocols, HIGH SPEED
Supported Families
Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Chapter 4: Functional Description
Clocking and Reset Structure
May 2011 Altera Corporation
High-Speed Transceiver Clocks
MII Interface Clock Domains
f
The cpri_clkout and cpu_clk clocks are assumed to be asynchronous. The cpu_clk
maximum value is constrained by f
speed grade.
The high-speed transceiver on the CPRI IP core CPRI interface uses the following
clocks:
■
■
■
■
In slave clocking mode, the gxb_pll_inclk clock connects to the pll_inclk input
signal of the Arria II GX, Arria II GZ, or Stratix IV GX transceiver’s PLL. The
gxb_refclk clock connects to the rx_cruclk input signal of the transceiver.
In master clocking mode, the CPRI IP core connects the gxb_refclk clock to the
pll_inclk input signal of the transceiver. The CPRI IP core does not use the
gxb_pll_inclk input signal. Refer to
page
In master clocking mode, the two transceiver signals pll_inclk and rx_cruclk are
implemented as a single input signal to the ALTGX megafunction, named
pll_inclk_rx_cruclk. However, the clocking mode implementation ensures that the
CPRI IP core signal is interpreted correctly.
For more information about the high-speed transceiver blocks, refer to
Arria II Device Handbook, to
and
The MII interface has the following two output clocks:
■
■
Both clocks have the same frequency as the cpri_clkout clock. The frequency
depends on the CPRI line data rate. Refer to
gxb_refclk—reference clock for the transceiver PLLs. In master clocking mode,
this clock drives both the receiver PLL and the transmitter PLL in the transceiver.
In slave clocking mode, this clock drives the receiver PLL.
gxb_cal_blk_clk—calibration-block clock.
reconfig_clk—dynamic reconfiguration block clock.
gxb_pll_inclk—input clock to the transmitter PLL in a CPRI IP core configured in
slave clocking mode. If the CPRI IP core is configured in master clocking mode, it
does not use this clock. In master clocking mode, you must tie this input to 0.
cpri_mii_txclk—clocks the MII interface transmitter module.
cpri_mii_rxclk—clocks the MII interface receiver module.
volume 3
4–6.
of the Stratix IV Device Handbook.
volume 2
MAX
of the Cyclone IV Device Handbook, or to
“Clock Diagrams for the CPRI IP Core” on
and can vary based on the device family and
Table 4–1 on page
CPRI MegaCore Function User Guide
4–12.
volume 2
volume 2
of the
4–5
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