IP-CPRI Altera, IP-CPRI Datasheet - Page 87

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Physical Layer Signals
Table 5–1. CPRI Interface
Table 5–2. CPRI Reference Clock and Main Reset Signals
Table 5–3. Layer 1 Error Signal
May 2011 Altera Corporation
gxb_rxdatain
gxb_txdataout
gxb_refclk
reset
reset_done
gxb_los
Signal
Signal
Signal
CPRI Data Signals
Layer 1 Clock and Reset Signals
Layer 1 Error Signal
Input
Direction
Input
Input
Output
Direction
This chapter describes all the top-level signals of the Altera CPRI IP core.
Table 5–1
the CPRI IP core. Refer to
Table 5–1
Table 5–2
Table 5–3
Input
Output
Direction
Loss of Signal (LOS) signal from small form-factor pluggable (SFP) module.
Transceiver reference clock. In master clocking mode, this clock generates the internal
clock cpri_clkout for the CPRI IP core and custom logic.
Transceiver reset. This reset is associated with the reconfig_clk clock. A reset controller
module propagates this reset to the CPRI IP core cpri_clkout clock domain as well.
reset can be asserted asynchronously, but must stay asserted at least one clock cycle and
must be de-asserted synchronously with the clock with which it is associated. Refer to
Figure 4–8 on page 4–14
of reset.
Indicates that the reset controller has completed the transceiver reset sequence.
through
lists the CPRI data link signals.
lists the Layer 1 clock and reset signals.
lists the Layer 1 error signal for the CPRI IP core.
Receive unidirectional serial data. This signal is connected over the CPRI link to the
txdataout line of the transmitting device.
Transmit unidirectional serial data. This signal is connected over the CPRI link to the
rxdatain line of the receiving device.
Table 5–6
Figure 4–9 on page 4–17
list the input and output signals of the physical layer of
for a circuit that shows how to enforce synchronous deassertion
Description
Description
Description
for details of the I/O signals.
CPRI MegaCore Function User Guide
5. Signals