IP-CPRI Altera, IP-CPRI Datasheet - Page 27

• Manufacturer Part Number: IP-CPRI
• Description: IP CORE - Common Public Radio Interface (CPRI)
• Manufacturer: Altera

Specifications of IP-CPRI

• Software Application: IP CORE, Interface And Protocols, HIGH SPEED
• Supported Families: Arria II GX, Cyclone IV GX, HardCopy IV, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces Overview
May 2011 Altera Corporation
CPRI Interface
CPU Interface
MAP Interface
Auxiliary Interface
f
f
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The CPRI interface complies with the CPRI Specification V4.1. The protocol is divided
into a two-layer hierarchy: physical layer and data link layer. The specification
describes three communication planes: user data, control and management (C&M),
and timing synchronization information.
More detailed information about the CPRI interface specification is available from the
CPRI website at www.cpri.info.
The CPRI IP core communicates with an on-chip or external processor through its
CPU interface. Use this interface to communicate control and management
information and for High-Level Data Link Controller (HDLC) or Ethernet
communication with an internal MAC block. An on-chip processor such as the Nios II
processor, or an external processor, can access the CPRI configuration address space
using this interface.
The CPU interface is implemented as an Avalon-MM slave interface. The Avalon-MM
slave executes transfers between the CPRI IP core and the user-defined logic in your
design. The CPU interface is the only Avalon-MM interface implemented by the CPRI
IP core.
For information about the CPU interface, refer to
page
For information about the Avalon-MM interface, refer to
The CPRI MAP interface comprises the individual antenna-carrier interfaces, or data
channels, through which the CPRI IP core transfers IQ sample data to and from the RF
implementation. The CPRI MAP interface is implemented as an incoming and an
outgoing Avalon-ST interface.
The Avalon-ST interface provides a standard, flexible, and modular protocol for data
transfers from a source interface to a sink interface.
For information about the CPRI MAP interface, refer to
Module” on page
For information about the Avalon-ST interface, refer to
The auxiliary (AUX) interface allows you to connect components together by
supporting a direct connection to a user-defined routing layer or custom mapping
block. You implement this routing layer, which is not defined in the CPRI V4.1
Specification, outside the CPRI IP core. The AUX interface supports the transmission
and reception of IQ data and timing information between an RE master and an RE
slave, allowing you to define a custom routing layer that enables daisy-chain
4–22.
4–22.
“CPU Interface Module” on
Avalon Interface
“CPRI MAP Interface
Avalon Interface
CPRI MegaCore Function User Guide
Specifications.
Specifications.
4–3