NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 55

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Status:
14.
Issue:
Status:
15.
Issue:
Status:
16.
Issue:
Status:
17.
Issue:
Status:
Specification Update
Note: 1-byte transactions on 16-bit PBI bus is not a supported case. Also, a PBI bus configured as 8-bit
No Fix. See the
UART, I
32-bit accesses
The UART, I
enables. Due to this functionality, accessing any of these unit memory mapped registers (MMR)
with any accesses less than 32-bits can result in corruption of the other bits in the 32-bit MMR. For
example, beginning with C-0 stepping, the GPOD register (located at FFFF_F788h) added new bit
functions to bits 10 and 11. When software does a byte access to GPOD, this could cause bits 10
and 11 to be written with incorrect data.
While most of these registers only implement the lower 8-bits (the upper three bytes are
‘reserved’), the recommendation is that all UART, I
as 32-bit registers. While it is desired that 32-bit accesses be performed, it is acceptable to access
with less than 32-bits, as long as all non-reserved bits are accessed. For purposes of future
expansion, 32-bit accesses are preferred.
No Fix. See the
Flash Wait States
The Address-to-Data wait state and Recovery Cycle wait state fields in Table 60 (PBBAR0) and
62 (PBBAR1) are incorrect in the Intel
Rev. 2.0, Vol. 2. The Address-to-Data wait state is actually one more than listed, and the Recovery
Cycle wait state is actually two more than listed. See Documentation Change #
information.
No Fix. See the
UART Interrupt Identification Register
The UART Interrupt Identification Register (UxIIR) is read by software to determine the type and
source of UART interrupts. This register gathers and priority encodes the various sources of UART
interrupts. The register is read after an interrupt occurs. Enabling and disabling of interrupts (via
the Interrupt Enable Register - UxIER or Modem Control Register - UxMCR) effects whether or
not the interrupt to the processor occurs. This does not effect the logging of the status of what is
happening in the UART. The UART operates in interrupt or polling mode. In polling mode, all
interrupts to the processor would be disabled.
No Fix. See the
Reads on 16-bit PBI bus operate as 32-bit
2-byte and 4-byte read transactions on the Peripheral Bus Interface (PBI) bus operate as burst reads
(in other words, two 16-bit read cycles). All the read transactions from the Intel XScale
PBI devices (in other words, SRAM, Flash, etc.) are translated to burst reads with burst size of 2,
even though there is no necessity to generate a burst transaction. Therefore, devices on the 16-bit
PBI bus should be configured as pre-fetchable.
does not operate this way.
No Fix. See the
2
C and GPIO memory mapped registers should be addressed with
2
C and GPIO units sit on a dedicated low speed internal bus that does not support byte
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
®
Lindsay I/O Processor Component Specification,
2
C and GPIO MMRs should only be accessed
9.
9.
9.
9.
9.
Specification Clarifications
Intel
®
80331 I/O Processor
8
for more specific
®
core to
55