NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 20

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel
Non-Core Errata
5.
Problem:
Implication:
Workaround:
Status:
6.
Issue:
Implication:
Workaround:
Status:
7.
Problem:
Implication:
Workaround:
Status:
8.
Problem:
Implication:
Workaround:
Status:
9.
Problem:
Implication:
Workaround:
Status:
20
®
80331 I/O Processor
Boundary Scan data gets inverted
Data driven in during boundary scan gets inverted during the capture phase. During parallel
loading on a pin, an external zero on data in gets inverted to one for data out. This is a violation of
the IEEE 1149.1 Specification.
Boundary scan cannot be used with A-1 stepping.
No workaround. Do not use boundary scan.
Fixed. Fixed in B-0 stepping. See the
BIU interrupt does not occur on Internal Bus Write Master Abort
Software developers be aware that an interrupt is not generated when the Bus Interface Unit gets
master aborted on an internal bus write.
When left undetected, it could cause data corruption.
The status bit needs to be polled by software.
Fixed. Fixed in B-0 stepping. See the
CRC value calculated by DMA unit is not compliant with iSCSI
Several issues with the CRC generation engine have caused it to not be compliant with iSCSI in
A-1 step.
CRC cannot be used with A-1 stepping.
No workaround.
Fixed. Fixed in B-0 stepping. See the
ATU Outbound Direct Window overlaps with PBI exception vectors
When the PBI exception vectors are enabled (PBCR.3), it claims addresses 00h-3fh. When the
ATU outbound direct window is enabled, it claims addresses 28h-7fffffffh. There is an overlap
between 28h-3fh, where both devices claim the internal bus transaction. For writes, this may not be
an issue, since the only transaction here is a posted write to the ATU. For reads, the PBI handles the
transaction as a single data phase disconnect, and the ATU internally handles it as a split
transaction.
The agent which issued the internal bus transaction does not claim the returning data, since the
transaction has been completed by the PBI. This causes the data from PCI to not be returned to the
issuing internal bus agent.
Consider address range of 28h-3Fh reserved.
Fixed. Fixed in B-0 stepping. See the
S_REQ64# Initialization Pattern Timing Violation in PCI-33 Mode
The PCI Local Bus Specification, Revision 2.3 states RST# to REQ64# Hold time is 0 ns minimum
and 50 ns maximum. The 80331 drives the REQ64# signal for three cycles after RST# deasserts.
Therefore, in PCI-33 mode, this is 90 ns, which violates the 50 ns maximum.
All other PCI and PCI-X modes are within the specification (i.e., PCI-66 is 45 ns).
Some PCI targets may not interpret the REQ64# signal correctly, causing it to operate in 32-bit
mode.
When running in PCI-33 mode, make sure PCI target can handle the extra 40 ns.
No Fix. Not to be fixed. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page 9
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Specification Update
9.
9.
9.
9.