NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 57

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Specification Update
Note: AAU source reads from PCI are not supported; only local memory can be used for this.
AAU result can be written directly to PCI host memory
The Application Accelerator Unit (AAU) can write results not only to local memory but also to the
PCI bus host memory via the ATU.
This feature can be applied to degraded RAID-5 reads, where the AAU result is the reconstructed
data for the host I/O read. The AAU can write its result to PCI; therefore, the degraded read XOR
result can be written directly to host memory. This eliminates the need for a DMA operation to
transfer the result from local memory to host memory via PCI.
Savings for the RAID application include the following:
No Fix. See the
PWRDELAY functionality during power sequencing
When the 3.3 V rail is powered on and the 1.5 V rail is powered off, the PWRDELAY input signal
drives out until the 1.5 V rail powers up. This is important to understand if still using the legacy
power-fail circuit, because it might cause other circuitry to function incorrectly. The proper usage
of PWRDELAY is described in specification change 11 (“PWRDELAY needs only a pull-up for
battery back-up mode”), which recommends that PWRDELAY be isolated from all circuitry and
tied to a 1.5 K pull-up resistor.
No Fix. See the
PBI lockout condition
When the core is in a tight loop writing to the PBI bus, while the DMA is doing a large block
transfer (for example, from SRAM, located on the PBI, to DDR memory), the DMA can be locked
out of accessing the PBI and the transaction will never complete.
If this condition occurs, use one of these workarounds:
1. Change the MTTR1 from 98h (default) to a lower value (such as 01h). A lower value allows the
DMA (or ATU which can also master a transaction to the PBI) to gain access to the PBI, because
the BIU is given shorter access for back-to-back BIU internal bus transactions.
2. Add a core read along with the core write, causing it to stall and preventing it from starving the
DMA.
3. Add NOPs or dummy instructions to ensure the loop spans greater than two cache lines.
4. Modify the loop such that the write is not done on every iteration.
No Fix. See the
Interleaving descriptors with D-0 AAU
The P+Q capability is enabled in the AAU globally (ACR.3), not on a descriptor by descriptor
basis.
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No DMA descriptor needs to be generated.
No DMA interrupt needs to be serviced.
Memory and internal bus bandwidth is saved (result write by AAU and read by DMA).
Read I/O is serviced faster (eliminates latency of DMA operation).
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
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Specification Clarifications
Intel
®
80331 I/O Processor
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