NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 10

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel
Summary Table of Changes
Non-Core Errata (Sheet 1 of 3)
10
No.
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11
1
2
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®
80331 I/O Processor
A-1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B-0
X
X
X
X
X
X
X
Steppings
C-0
X
X
X
X
X
C-1
X
X
X
X
X
D-0
X
X
X
X
X
D-1
X
X
X
X
X
Page
19
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Status
No Fix
No Fix
No Fix
No Fix
No Fix
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
CAS latency of three not supported for DDR-II On-Die
Termination (ODT)
Upper PCI signals on Secondary PCI bus are not driven
low during reset
Memory Controller Unit does not properly support 32-bit
memory configurations
Legacy Power Fail Mechanism does not work
Boundary Scan data gets inverted
BIU interrupt does not occur on Internal Bus Write Master
Abort
CRC value calculated by DMA unit is not compliant with
iSCSI
ATU Outbound Direct Window overlaps with PBI exception
vectors
S_REQ64# Initialization Pattern Timing Violation in PCI-33
Mode
PCI-66 Mode violates PCI AC Timings
Reserved bits in the Modem Status Register incorrectly
generate interrupts
P_REQ# not de-asserted during idle
Chassis/Slot PCI Extended Capability is not valid
SDCR0.2 implemented as ‘Reserved’
32-bit region missing proper address decode
S_GNT[3:2]# outputs are not pulled high when Bridge is
disabled.
Split Transaction Commitment limit register mechanism, in
the PCI-X bridge, does not operate as implied by the PCI-X
Addendum to the PCI Local Bus Specification,
Revision 1.0a
Watchdog time-outs by the PCI-X bridge may cause data
corruption
Discard timer expiration on delayed read can cause data
corruption or deadlock when data is still being received on
target bus
Configuration cycle attribute parity error signaled
incorrectly by PCI-X bridge
Transactions are buffered during Secondary Reset
Primary bus pin mode behavior incorrect during reset in the
80331 no bridge mode
P_REQ# pin mode behavior when in the 80331 no bridge
mode
Master abort after data transfer within a single ADB on
PCI-X to PCI-X read block transactions may cause data
corruption or deadlock
Errata
Specification Update