NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 29

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

37.
Problem:
Implication:
Workaround:
Status:
Specification Update
Note: 1) The case where this happens is where the core memory port is enabled and there is a cache line
Intel XScale
The Intel XScale
Unit (BIU), which manages traffic in two directions; a general path to the Flash and PCI-X
interfaces (as well as internal units) and a private path to DDR memory controller. There is a
boundary condition for returning data, specifically for code fetches from Flash or host memory
colliding with private DDR read data. At the wrong clock alignment, the BIU corrupts the
returning code with the DDR data. This results in arbitrary code returned to the core, resulting in
lockup or other unpredictable core behavior. The following describes one scenario of how this
condition can occur:
fill (instruction or data) that executes through the internal bus (Flash/PCI/etc., transactions, not
DDR transactions) and any size fetch to DDR through the direct port to DDR memory controller.
The timing has to be such that the cache line fill from the internal bus must beat the DDR return by
1 clock cycle.
2) The scenario given above is just one example of what excites this condition and is by no means
the only scenario that excites this condition.
This results in a lockup or other unpredictable core behavior.
For A-x and B-0 silicon the only reliable workaround is for software to turn off the core to the
DDR Memory Controller port, redirecting DDR accesses through the Internal Bus interface with
other transactions. This prevents the core lockup condition but at a cost to performance.
Fixed. Fixed in C-0 stepping. See the
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The Intel XScale
internal bus to the Flash interface unit and out to Flash memory.
While this is happening, the Intel XScale
data transactions through a second private path, directly to the DDR Memory Controller.
These data transactions are a series of cache line writes to DDR and reads from DDR.
The original instruction fetch is returned from the Flash interface unit back to the core with the
critical instruction first (critical word first).
One clock after the instruction cache line is being returned to the Intel XScale
the data transactions returns from the DDR memory controller.
The BIU switches to handle the higher priority DDR return.
The instruction cache line that was being returned from the Flash interface is only partially
returned to the Intel XScale
The data cache line from the DDR memory controller is then returned to the Intel XScale
core in its entirety.
The Intel XScale
line (since the critical instruction was returned first, the core can continue).
The five instructions that were returned are executed by the Intel XScale
then stalls waiting for the sixth, seventh and eighth instruction to be returned from the initial
cache line fill.
The BIU continues to return any outstanding transactions unaware that the instruction cache
fetch was not fully returned.
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Core lockup condition
core fetches code and data through an internal switch called the Bus Interface
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core fetches an instruction cache line, which is executed through the
core then starts executing the instructions that were fetched in the cache
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core (five of the eight instructions).
Table , “Summary Table of Changes” on page
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core is scrubbing the DDR clean with a series of
Intel
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80331 I/O Processor
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core and the core
Non-Core Errata
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9.
core
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one of
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