NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 14
NQ80331M667 S L824
Manufacturer Part Number
NQ80331M667 S L824
Description
Manufacturer
Intel
Datasheet
1.NQ80331M667_S_L824.pdf
(67 pages)
Specifications of NQ80331M667 S L824
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Intel
Summary Table of Changes
Specification Changes
14
No.
10
12
13
14
15
16
17
18
19
20
21
22
11
®
1
2
3
4
5
6
7
8
9
80331 I/O Processor
A-1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B-0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Steppings
C-x
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D-0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D-1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Page
47
47
47
47
47
47
48
48
48
48
48
48
48
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48
49
49
49
49
49
50
50
Status
Fixed
Doc
Doc
Doc
Doc
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HPI# (High Priority Interrupt) is a maskable interrupt
PCIODT_EN Reset Strap Signal
LOCK# functionality has been de-featured
Watchdog Timer and Retry Timer has been de-featured
P_GNT# and P_REQ# signals have new ball locations on
B-0
Peripheral Performance Monitor Unit has been de-featured
Processor Device ID has been removed
1.5K pull-down required on AD[15] of the PBI bus
OCD and Receive Enable calibration de-featured
New Watchdog Timer (WDT) functionality in B-0 stepping
PWRDELAY needs only a pull-up for battery back-up mode
ARB_EN signal has been de-featured
Intel® 80331 I/O Processor Design Guide change for
Unbuffered DDR-I dual-banked DIMMs
DDRRES2 can be pulled down to reduce current during
self-refresh
Intel® 80331 I/O Processor Design Guide change for
Peripheral Bus Interface (PBI)
Intel® 80331 I/O Processor Design Guide change for
PCI/-X busses
Internal bus operates at 333 MHz for D-0 stepping
Application Accelerator Unit enhanced for D-0 stepping
Recommended DLL register values
DDR-II JEDEC initialization sequence includes writes to
EMRS2 and EMRS3
Case temperature (Tcase) change
Internal Clock Misalignment.
Specification Changes
Specification Update
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