NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 63

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

9.
Problem:
Workaround:
Table 236.
Specification Update
31:28
26:24
22:20
19:18
17:16
15:14
13:12
11:10
09:08
Bit
27
23
Attributes
Attributes
IOP
PCI
Default
000 2
000 2
00 2
01 2
00 2
00 2
00 2
00 2
0H
0 2
0 2
Intel XScale
FFFF E504H
SDCR0 and SDCR1 register updates
The SDCR0
DDR SDRAM Control Register 0 - SDCR0 (Sheet 1 of 2)
rw
na
31
na
rw
RAS: Active to Precharge duration in MCLK periods
Equation 7: RAS = tRAS - 1
where tRAS is from SPD
Reserved
RP: Precharge Command Period in MCLK periods
Equation 8: RP = tRP - 1
where tRP is from SPD
Reserved
RCD: Active to Read, Active to Write Period in MCLK periods
Equation 9: RCD = tRCD - 1
where tRCD is from SPD
Reserved
EDP: Data Path Latency in MCLK periods
This field should be programmed to 10
Reserved
WDL: Write Data Latency in MCLK periods used by the Memory Controller state machine. See
Equation
11 = reserved
where tCAS is from SPD
Reserved
CAS: CAS Latency: Indicates the CAS Latency used by the Memory Controller state machine.
Encoded value based on tCAS from SPD
• 00 = 0 MCLK periods (tCAS = 2.5) - (DDR-I Type only)
• 01 = 1 MCLK period (tCAS = 3) - (DDR-II Type only) - not supported
• 10 = 2 MCLK periods (tCAS = 4) - (DDR-II Type only)
• 00 = reserved
• 01 = 2.5 MCLK periods (DDR-I Type only)
• 10 = 3 MCLK periods (DDR-II Type only) - not supported
• 11 = 4 MCLK periods (DDR-II Type only)
rw
na
®
core Local Bus Address
na
rw
28
(Table
na
rv
11.
rw
na
236) and SDCR1
rw
na
rw
na
24
na
rv
na
rw
rw
na
rw
na
20
na
rv
(Table
na
rv
2.
na
rw
237) register description needs to be updated.
rw
na
16
Description
na
rv
na
rv
rw
na
na
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
12
na
rv
na
rv
na
rw
rw
na
Intel
8
Documentation Changes
na
rv
®
na
rv
80331 I/O Processor
rw
na
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
na
rw
4
na
rv
na
ro
rw
na
rw
na
0
63