NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 15

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Specification Clarifications
Specification Update
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Steppings
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Status
No Fix
No Fix
No Fix
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Fixed
64 MB and 2 GB DDR333 capacities not to be tested in post-silicon
validation
DDR-II 400 Unbuffered DIMMs are not supported
Interrupt behavior in the 80331 no bridge mode
Memory map for 2 GByte of DDR memory
Back to back MCU MMR reads
Write requirements for the Peripheral Bus Interface
PCI-X Status Register during PCI mode
M_RST# driven to DDR-II or DDR-I voltage levels
BIU master abort causes two interrupts on reads.
Reset Internal Bus (PCSR.5) usage
No Bridge Mode (BRG_EN) validation
Potential race condition with Interrupt Controller Unit status bits
Bus Interface Unit follows PCI ordering rules
UART, I
addressed with 32-bit accesses
Flash Wait States
UART Interrupt Identification Register
Reads on 16-bit PBI bus operate as 32-bit
Embedded Design Usage Model - Secondary PCI bus only
3.3 V to 1.5 V leakage
Accessing “reserved” registers in “no bridge” mode
Power plane isolation for Battery Back-Up (BBU) mode
AAU result can be written directly to PCI host memory
PWRDELAY functionality during power sequencing
PBI lockout condition
Interleaving descriptors with D-0 AAU
RCVDLY setting for DDR-I memory
ATUBAR3 Functionality
VREF isolation for Battery Back-up (BBU) mode
I2C Unit Enabling
DMA transactions from local memory to a conventional PCI target
can complete out of order
SBR1 Programming with Bank 1 Unpopulated
32-bit Writes to Unaligned 64-bit Addresses are Promoted to 64-bit
Aligned Writes
Case Temperature Clarification.
2
C and GPIO memory mapped registers should be
Specification Clarifications
Summary Table of Changes
Intel
®
80331 I/O Processor
15