NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 66

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel
Documentation Changes
10.
Problem:
Workaround:
Affected Docs: Intel
11.
Problem:
Workaround:
Affected Docs: Intel
12.
Problem:
Workaround:
Affected Docs: Intel
66
®
80331 I/O Processor
Power sequence timing
Section 9.1 of the Intel
requirement between VCC33 and VCC15, but does not mention any timing parameters.
The following are the power sequencing requirements that must be followed:
Updated Peripheral Bus Interface (PBI) timings
Table 27 in the 80331 datasheet must be updated.
Table 27 must have the following values:
ATU PM_CAP[5] text must be updated
Table 140, bit[5] reads as follows: DSI – This field is set to 0
device specific initialization sequence following the transition to the D0 uninitialized state.
It must be changed to the following: DSI – This field is set to 0
require a device specific initialization sequence following the transition to the D0 uninitialized
state.
1. The 80331 requires that the VCC33 voltage rail be no less than 0.5 V below VCC15 (absolute
2. When a voltage regulator solution is used, which shunts VCC15 to ground while VCC33 is
3. The maximum allowed time between VCC33 and VCC15 ramping is 525 ms. There is no
•
•
•
•
•
•
•
•
•
voltage value) at all times during operations, including during system power-up and
power-down. In other words, the following must always be true:
powered, the maximum allowable time that VCC15 can be shunted to ground while VCC33 is
fully powered is 20 ms.
minimum sequencing time requirement.
®
Tah1 – ALE high time = 15 ns minimum
Tav1 – ALE high to address valid = 0 ns maximum
Tah2 – ALE low to address invalid = 15 ns maximum
Tas1 – Address valid to ALE low = 15 ns minimum
Tao1 – ALE low to POE# low = 0 ns minimum
Taw1 – ALE low to PWE# low = 15 ns minimum
Tah3 – PWE# high to data invalid = 15 ns minimum
Tas2 – Data valid to PWE# high = 6 0ns minimum
Tac1 – ALE low to PCE[1:0]# low = 15 ns minimum
®
®
— VCC33 >= (VCC15 - 0.5 V). This can be accomplished by placing a diode (with a voltage
80331 I/O Processor Design Guide
80331 I/O Processor Datasheet
80331 I/O Processor Developer’s Manual
drop < 0.5 V) between VCC15 and VCC33. The Anode is connected to VCC15 and the
Cathode is connected to VCC33.
®
80331 I/O Processor Design Guide describes the power sequence
2
meaning that this function requires a
2
meaning that this function does not
Specification Update