NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 13

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Core Errata
Specification Update
No.
1
2
3
4
5
6
7
8
A-1
X
X
X
X
X
X
X
X
B-0
X
X
X
X
X
X
X
X
Steppings
C-0
X
X
X
X
X
X
X
X
D-0
X
X
X
X
X
X
X
X
D-1
X
X
X
X
X
X
X
X
Page
43
43
44
44
45
45
46
46
Status
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Abort is missed when lock command is outstanding
Aborted Store that Hits the Data Cache May Mark Write-Back
Data as Dirty
Performance Monitor Unit event 0x1 can be incremented
erroneously by unrelated events
In Special Debug State, back-to-back memory operations —
where the first instruction aborts — may cause a hang
Accesses to the CP15 ID register with opcode2 > 0b001
returns unpredictable values
Disabling and re-enabling the MMU can hang the core or
cause it to execute the wrong code
Updating the JTAG parallel registers requires an extra TCK
rising edge
Non-branch instruction in vector table may execute twice after
a thumb mode exception
Summary Table of Changes
Errata
Intel
®
80331 I/O Processor
13