NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 27

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Specification Update
ATU passing rules operation in PCI mode
When the secondary PCI bus is in PCI bus mode, the PCI passing rule enforcement logic within the
ATU, allows a read completion to pass write data; until at least four inbound delayed reads,
inbound configuration writes, inbound configuration reads, or any combination of these have
occurred from the PCI bus.
This issue causes a deadlock condition in legacy devices, which contain shared read and write data
queues, where the device allocates the data buffer for the requested delayed read data and is also
being addressed by the outbound ATU write data. This ATU functionality does not exist in PCI-X
mode.
Use the secondary PCI bus in PCI-X mode.
When the secondary PCI bus is in PCI mode, configuration retry is enabled, and the legacy buffer
allocating device is present in the system, the ATU must not issue writes to that device until the
configuration cycles or reads have completed. When this situation cannot be achieved by the host,
the ATU can be momentarily programmed in loopback mode and issue delayed reads to itself. This
workaround is only required when the ATU is sending upstream traffic at the same time as the host
is configuring it. This should not happen since the ATU needs to wait for the driver to be enabled
after enumeration completes.
This erratum does not occur when configuration retry is deasserted at power on and the host meets
the above configuration cycles.
No Fix. Not to be fixed. See the
S_INT[D:A]# pull-ups disabled by Internal Bus Reset
During power-on or anytime the internal bus is reset, the S_INT[D:A]# interrupt inputs are asserted
as the on-die termination (ODT) gets disabled.
This situation causes floating/asserted interrupts to the 80331, during power-on or anytime the
internal bus is reset.
Need external pull-ups on the S_INT[D:A]# pins.
Fixed. Fixed in C-0 stepping. See the
MCU Preemption Control does not properly manage the byte count
During a transfer, the MCU tracks the byte count to determine when a transfer can be preempted.
When preemption is enabled, a preempted transfer that is resumed does not transfer the full
remaining byte count of data.
Can cause data corruption when preemption control is enabled.
Do not enable preemption control. Keep the default setting of the MCU Preemption Control
Register (MPCR, FFFF E540h) bits 3-0 as 0h.
Fixed. Fixed in C-0 stepping. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Intel
®
80331 I/O Processor
9.
Non-Core Errata
9.
9.
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