NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 53

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

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Specification Update
Note: When central resource functionality is required, then the 80331 needs to be used with the bridge
Reset Internal Bus (PCSR.5) usage
PCI bus data corruption can occur when the reset internal bus bit is not used correctly. PCSR.5 can
be used to reset the internal bus. This resets all memory mapped registers and the ATU
configuration header space. This bit is read/write capable from both the internal bus and PCI bus.
For both PCI and PCI-X modes, make sure the following steps occur when setting PCSR.5:
No Fix. See the
No Bridge Mode (BRG_EN) validation
The BRG_EN signal (0 = no bridge, muxed on AD[0]) is used to disable the internal bridge, in
order to operate as an I/O processor with a single PCI-X interface. This feature is not to be
validated until after PTQ (prototype qualification).
enabled.
No Fix. See the
Potential race condition with Interrupt Controller Unit status bits
There is a slight lag in the time it takes between clearing a status bit inside the unit and the
corresponding bit in the Interrupt Controller Unit Status Register getting cleared. This has the
potential of generating a false interrupt, meaning that the Intel XScale
handler is not able to find any source reported in the ICU registers. This condition can be avoided
by adding a read from any ICU register after the bit is cleared in the local unit before returning
from the interrupt handler. The data from this read can be ignored, but the read itself creates
enough latency to allow the updated status to propagate to the ICU
No Fix. See the
1. Clear Bus Master (ATUCMD.2) Enable and Memory Enable (ATUCMD.1).
2. Wait for both the outbound (PCSR.15) and inbound (PCSR.14) read transaction queue busy
3. Make sure no PCI configuration read/write cycles targeting the ATU are in progress, except
4. Set the Reset Internal Bus bit.
5. Wait for 40 PCI clocks.
bits to clear.
the reset configuration write, when applicable.
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
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Specification Clarifications
Intel
®
®
core is interrupted but the
80331 I/O Processor
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