NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 64

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel
Documentation Changes
Table 236.
64
07:06
05:04
Bit
03
02
01
00
®
80331 I/O Processor
Attributes
Attributes
external state
MEM_TYPE
Varies with
at PCI bus
IOP
PCI
Default
reset
00 2
00 2
0 2
0 2
0 2
Intel XScale
FFFF E504H
of
DDR SDRAM Control Register 0 - SDCR0 (Sheet 2 of 2)
rw
na
31
na
rw
Reserved.
ODT Termination Value: Determines the termination value of the On Die Termination for both Banks
(controlled by ODT[1:0]). Applies to DDR-II SDRAM memory type only.
Reserved
DDR Type: Identifies the selected DDR generation of SDRAM based on the MEM_TYPE reset strap.
0 = DDR-II (supported speed of 400 MHz) - MEM_TYPE Deasserted.
1 = DDR (supported speed of 333 MHz) - MEM_TYPE Asserted.
Data Bus Width: Indicates the width of the data bus. See
page
0 = 64 bits
1 = 32 bits
DIMM Type: Selects unbuffered or registered DIMM operating modes for the MCU.
0 = Unbuffered*
1 = Registered
NOTE: Unbuffered DDR SDRAM memory subsystems will use the Unbuffered mode.
• 00 Disabled
• 01 75 ohm
• 10 150 ohm
• 11 reserved
rw
na
®
core Local Bus Address
na
rw
458.
28
na
rv
rw
na
na
rw
rw
na
24
na
rv
na
rw
rw
na
na
rw
20
na
rv
na
rv
na
rw
rw
na
16
Description
na
rv
na
rv
rw
na
na
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
12
Section 8.3.3.4, “32-bit Data Bus Width” on
na
rv
na
rv
na
rw
rw
na
8
na
rv
na
rv
rw
na
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
na
Specification Update
rw
4
na
rv
na
ro
na
rw
rw
na
0