NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 54

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel
Specification Clarifications
13.
Issue:
54
®
80331 I/O Processor
Bus Interface Unit follows PCI ordering rules
The Core Bus Interface Unit orders transactions based on PCI rules. This allows outgoing writes to
pass incoming reads. For most devices on the internal bus, this does not cause problems since the
devices function asynchronously with respect to each other. For transactions between the Intel
XScale
This code could potentially load the register r3 with the value 0x55555555 since the store in line 6
may pass the load in line 5. This only happens with transactions on the internal bus.
The MCU core port enforces strict ordering and does not exhibit this behavior. If the MCU core
port is used, then this issue will not occur.
When caching is enabled, then the initial read will initiate a cache-line fill. The subsequent write is
pended in the Intel XScale
issue does not occur.
When caching is disabled, and the caching policy is stall-until-complete (X=0, C=0, B=0), this
issue does not occur. For other MMU settings with caching disabled, the issue can occur.
Specifically regions with data cache and write buffer policies of bufferable (X=0, C=0, B=1) or
coalescing-disabled-bufferable (X=1, C=0, B=1) are vulnerable to this issue. In addition, regions
configured as write through (X=0, C=1, B=0) are also vulnerable to this issue.
In addition, if caching is enabled in the MMU page tables, but the DCache is disabled in the CP15
ARM Control Register, then the effective caching policy is bufferable and this reordering must be
accounted for.
It is important to realize that any code which accesses memory spaces on the internal bus need to
account for this possibility. Code which dynamically disables cache (i.e. - flash programming
routines) needs to ensure that the caching policy for the appropriate memory region is set to “stall
until complete” until the cache is re-enabled.
The simplest scenario to reproduce this is two back-to-back function calls, for example:
0: ldr r0, =0x40000
1: ldr r1, =0xaaaaaaaa
2: ldr r2, =0x55555555
3: str r1, [r0]
4: … <time-delay to allow the previous transactions to complete>
5: ldr r3, [r0]
6: str r2, [r0]
®
main:
fun1:
fun2:
core and memory via the internal bus, this can result in unexpected data. For example:
bl
bl
…
…
…
stmfd
ldmfd
stmfd
ldmfd
fun1
fun2
®
sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
sp!, {r4, fp, ip, lr}
sp!, {r4, fp, ip, pc}
core until the line fill and the ldr instruction complete. In this case, this
Specification Update