NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 48

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel
Specification Changes
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80331 I/O Processor
Note: In some applications PWRDELAY may control other board logic. Before making this change,
Processor Device ID has been removed
The Processor Device ID (PDIR) at FFFF E780h is suppose to mirror the JTAG ID, but instead has
a value of 0x0. This register is not to be fixed in future steppings, since there are other registers that
can be read to determine processor type and revision information.
1.5K pull-down required on AD[15] of the PBI bus
In order to prevent secondary PCI clock instabilities, make sure AD[15] of the PBI bus has a 1.5 K
pull-down.
OCD and Receive Enable calibration de-featured
The ability to adjust the electrical interface to account for out of specification DDR-II DIMMs
using OCD (off-chip driver) and receive enable calibration, is no longer a supported feature.
New Watchdog Timer (WDT) functionality in B-0 stepping
Watchdog timer (WDT) expiration can either generate a chip reset or a core interrupt. Added
Watchdog timer interrupt control to the following register bits: INTCTL0.17, INTSTR0.17,
IINTSRC0.17, FINTSRC0.17, IPR1.3:2
Control for WDT reset or interrupt generation is done by the interrupt mask bit, INTCTL0.17.
When clear (default), the WDT generates a reset. When set, the WDT generates an interrupt to the
core. These functions are mutually exclusive. The WDT is disabled by default see the developers
manual for the enabling sequence.
PWRDELAY needs only a pull-up for battery back-up mode
The I
PWRDELAY circuit to be simplified to a single pull-up resistor, to enable battery back-up mode.
PWRDELAY must be isolated from all other circuitry, and only a 1.5K pull-up to 3.3 V is required.
When battery back-up is not required, PWRDELAY should have a 1.5 K pull-down resistor.
make sure the other logic is not adversely impacted.
ARB_EN signal has been de-featured
The ARB_EN reset strap, muxed on AD[1], has been de-featured from the 80331. When using ‘no
bridge’ mode (BRG_EN=0), ARB_EN needs to be pulled low.
Intel® 80331 I/O Processor Design Guide change for Unbuffered DDR-I
dual-banked DIMMs
The latest routing guidelines for unbuffered DDR-I dual-banked DIMMs are available upon
request and is included in the next revision of the design guide.
Update - These routing guidelines were added to the October 2004 release of the 80331 design
guide (273823-002)
DDRRES2 can be pulled down to reduce current during self-refresh
DDRRES2 is used as compensation for DDR-II OCD. Since OCD is not supported in the 80331
(see Specification Change #9), then DDRRES2 can be pulled down to reduce current draw during
self-refresh mode.
Intel® 80331 I/O Processor Design Guide change for Peripheral Bus
Interface (PBI)
The latest routing guidelines for the Peripheral Bus Interface (PBI) are available upon request and
included in the next revision of the Intel
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C bus has been removed from the processor reset equation (see erratum #35). This allows the
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80331 I/O Processor Design Guide.
Specification Update