NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 11

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Non-Core Errata (Sheet 2 of 3)
Specification Update
No.
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A-1
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Steppings
C-0
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D-0
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Status
No Fix
No Fix
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Fixed
Fixed
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Fixed
Boundary scan multi-chip module implementation
Auto refresh command also generates a Precharge All
command on DDR bus
SERR# set to incorrect voltage
M66EN set to incorrect voltage
P_INT[D:A]# not operating correctly
Secondary bus may not initialize correctly at 100 MHz
PCI-X or 133 MHz PCI-X
Coalesced writes to 32-bit memory can cause data
corruption
ATU passing rules operation in PCI mode
S_INT[D:A]# pull-ups disabled by Internal Bus Reset
MCU Preemption Control does not properly manage the
byte count
I
VPD Data Register bit 19 is not read/write
Intel XScale
32-bit region write corrupts ECC immediately after 64-bit
Read-Modify-Write
Reset straps incorrectly sampled on the secondary reset
PCI-X to PCI Memory Read double-word near 1MB
boundary may cause the system to hang
PCI-X to PCI Memory Read Block across 1MB boundary
may cause data corruption
DMA CRC result is byte reversed
CRC corruption on PCI-to-local DMA transfers
Byte Count Modified bit set to 1
Corrupted byte count and data when crossing 1 MByte
boundary in PCI-X to PCI mode
PCI-X to PCI Memory Read with 4 K byte count and
unaligned starting address
VCCDDR (VCC25/VCC18) Current Spike
Bridge PCI ordering rule violation
ATU claims PCI commands 8 and 9 when issued as Dual
Address Cycle (DAC)
Secondary bus PCI RST# pulse prior to the rising edge of
P_RST#
Slow edge rates observed when 80331 is driving the
primary bus
Enabling the core-to-memory port can cause a stall
condition
2
C unit hang condition
®
Core lockup condition
Summary Table of Changes
Intel
Errata
®
80331 I/O Processor
11