NQ80331M667 S L824 Intel, NQ80331M667 S L824 Datasheet - Page 28

• Manufacturer Part Number: NQ80331M667 S L824
• Manufacturer: Intel

Specifications of NQ80331M667 S L824

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Intel
Non-Core Errata
35.
Problem:
Implication:
Workaround:
Status:
36.
Problem:
Implication:
Workaround:
Status:
28
®
80331 I/O Processor
I
When a processor reset occurs, the 80331 does not properly detect an idle condition on the I
potentially causing the I
writing a 0 on the SDA signal when reset is asserted. The SCL signal goes high, but SDA remains
low, signaling that the bus is still busy. Warm reset does not clear up this condition; only a cold
reset (power-on) resolves the I
The I
Since this is fixed in the C-0 stepping, this workaround must be implemented only when I
issues are preventing proper usage of A-2 and B-0 parts. The recommended workaround for A-1
and B-0 parts involves both a hardware and software change. In hardware, tie GPIO pins to the
SCL signals; then in the initialization software, the GPIO pins must toggle the SCL signals to bring
the slave I
an external tristate buffer on SCL lines, or by using two GPIO signals and no external logic to
allow unlocking the I
PWRGD.
Fixed. Fixed in C-0 stepping. See the
In the C-0 stepping, the I
GPOD[11:10] to toggle SCL[1:0]. Bit[11] and bit[10] of the GPOD register are writable. When
GPOD[11] is high, SCL[1] is driven low. When GPOD[10] is driven high, SCL[0] is driven low.
I
can hang when a reset happens during the reading of a 0 from an external I
software is required to toggle the I
GPOD bit[11] and bit[10] can be used to unhang the bus by creating a 100 K (5 ms high and low
time) or 400 K (1.25 ms high and low time) clock pulse.
Also, since the I
circuit is no longer needed. Only a 1.5 KΩ pull-up to 3.3 V is required on PWRDELAY. See
Specification Change 11,
page
VPD Data Register bit 19 is not read/write
VPD (Vital Product Data) is an extended capability of the ATU. Bit 19 of the VPD Data Register
(FFFF_E1BCh) was implemented as RC (read clear) instead of RW (read/write).
This is application dependant as VPD provides the system with information that uniquely identifies
hardware and, potentially, software elements of a system.
When the VPD feature is needed, care must be taken to mask bit 19.
No Fix. Not to be fixed. See the
2
2
C is no longer in the processor reset equation for the internal bus (that it, MRST), so the I
C unit hang condition
2
48.
C bus stays in a hang condition indefinitely
2
C devices out of the locked condition. This can be done by using one GPIO signal and
2
C bus has been removed from the processor reset equation, the PWRDELAY
2
C bus. Also, the external PWRDELAY circuit must use S_RST#, instead of
2
2
C unit to hang indefinitely. This occurs only when an I
“PWRDELAY needs only a pull-up for battery back-up mode” on
C bus lock condition can be cleared by software doing a toggle of the
2
C bus hang.
Table , “Summary Table of Changes” on page
2
C clock signals (at least eight times) before I
Table , “Summary Table of Changes” on page
2
C slave. Therefore, the
Specification Update
9.
2
2
C is enabled.
C slave device is
9.
2
2
2
C hang
C bus
C bus,