DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 2

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview
1-2
This data sheet uses the following conventions:
Note: *Values for V
“deasserted”
Examples:
OVERBAR
“asserted”
CLKOUT
EXTAL
PINIT/NMI
RESET
Timer
Triple
Generator
Internal
Switch
Six Channel
Generation
DMA Unit
Data
Clock
IL
Bus
Address
PLL
, V
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active
when low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Unit
OL
(SPDIF)
Signal/Symbol
2
, V
DAX
IH
Controller
Program
, and V
Interrupt
PIN
PIN
PIN
PIN
16
Interface
Figure 1-1 DSP56362 Block Diagram
Host
OH
DSP56362 Technical Data, Rev. 4
are defined by individual product specifications.
Expansion Area
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Peripheral
Data Sheet Conventions
Controller
12
Program
ESAI
Decode
Logic State
False
False
5
True
True
SHI
Generator
Bootstrap ROM
Program
Address
Program RAM/
Program ROM
Instruction
3072 × 24
30K × 24
192 × 24
Cache
DSP56300
24-Bit
Core
DDB
YDB
XDB
PDB
GDB
24 ¥ 24 + 56 Æ 56-bit MAC
DAB
Two 56-bit Accumulators
YAB
XAB
PAB
56-bit Barrel Shifter
Signal State
5632 × 24
Deasserted
Deasserted
6144 ×
X Data
Asserted
Asserted
RAM
ROM
24
Data ALU
6144 × 24
Y Data
5632 ×
RAM
ROM
24
DRAM/SRAM
I - Cache
Interface
Data Bus
Control
External
Address
External
Switch
Expansion
Switch
Bus
Memory
Bus
&
OnCE™
Mngmnt.
Freescale Semiconductor
Area
Power
JTAG
V
V
Voltage*
V
V
AA0456G
IH
IH
IL
IL
Control
Address
/ V
/ V
/ V
/ V
Data
18
11
OL
OH
OH
OL
24
6