DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 87

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. T
(F
Choosing HRS = 0 gives
Thus the HDM[7:0] value should be programmed to $38 (=56).
Freescale Semiconductor
.
SCL
= 100 KHz (i.e. T
HREQ
SDA
SCL
Stop
172
173
174
188
Start
Filters bypassed
Narrow filters enabled
Wide filters enabled
T
177
SCL
I
Table 3-23 SCL Serial Clock Cycle generated as Master
2
CCP
HDM 7 0 :
= 10µs), T
176
=
[
189
171
10µs 2.5
MSB
179
]
DSP56362 Technical Data, Rev. 4
R
=
–
= 1000ns), with filters bypassed
Figure 3-39 I
8930ns
186
C
178
×
= 10ns), operating in a standard-mode I
10ns 45ns 1000ns
175
⁄
2 (
T
T
T
I
I
I
–
2
2
2
2
CCP
CCP
CCP
×
184
C Timing
10ns
+ 2.5 × T
+ 2.5 × T
182
+ 2.5 × T
180
LSB
–
×
Serial Host Interface (SHI) I
8 ) 1
C
C
C
–
+ 45ns + T
+ 223ns + T
+ 135ns + T
=
=
ACK
55.8
8930ns
R
R
R
187
183
Stop
2
C environment
2
C Protocol Timing
AA0275
3-61