DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 64

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Memory Expansion Port (Port A)
3.10.3
3-38
198
199
200
201
202
203
204
205
206
207
208
No.
TA valid to CLKOUT high (setup time)
RAS
CAS
CLKOUT high to address, and AA valid
CLKOUT high to address, and AA invalid
CLKOUT high to TA invalid (hold time)
CLKOUT high to data out active
CLKOUT high to data out valid
CLKOUT high to data out invalid
CLKOUT high to data out high impedance
Data in valid to CLKOUT high (setup)
CLKOUT high to data in invalid (hold)
CLKOUT high to RD assertion
WR
Synchronous Timings (SRAM)
Table 3-17 External Bus Synchronous Timings (SRAM Access)
Characteristics
177
190
170
162
189
Figure 3-19 DRAM Refresh Access
DSP56362 Technical Data, Rev. 4
4
4
157
163
165
Expression
0.25 × T
0.25 × T
0.75 × T
0.25 × T
0.25 × T
0.25 × T
0.25 × T
C
C
C
+ 4.0
+ 4.0
+ 4.0
C
C
C
C
162
2
,
3
1
Freescale Semiconductor
Min
2.5
4.0
0.0
2.5
3.3
2.5
4.0
0.0
8.2
—
—
100 MHz
AA0478
Max
11.5
6.5
6.5
2.5
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns