DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 49

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
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139 CAS deassertion pulse width
140 Column address valid to CAS assertion
141 CAS assertion to column address not valid
142 Last column address valid to RAS deassertion
143 WR deassertion to CAS assertion
144 CAS deassertion to WR assertion
145 CAS assertion to WR deassertion
146 WR assertion pulse width
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
149 Data valid to CAS assertion (write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
154 RD deassertion to data not valid
155 WR assertion to data active
156 WR deassertion to data high impedance
No.
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56362.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
read-after-read or write-after-write sequences).
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of
page-access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Table 3-11 DRAM Page Mode Timings, Three Wait States
Characteristics
6
DSP56362 Technical Data, Rev. 4
Symbol
t
t
t
t
t
t
t
t
t
t
WCH
t
WCS
t
CAH
RCS
RCH
RWL
CWL
t
t
ROH
t
t
ASC
RAL
WP
DH
GA
CP
DS
GZ
External Memory Expansion Port (Port A)
1.25 × T
2.25 × T
3.75 × T
3.25 × T
1.25 × T
0.75 × T
0.75 × T
1.5 × T
2.5 × T
3.5 × T
0.5 × T
2.5 × T
3.5 × T
2.5 × T
Expression
4 × T
1, 2, 3, 4
100 MHz:
100 MHz:
100 MHz:
0.25 × T
T
C
− 4.0
C
C
C
C
C
C
C
C
C
C
C
C
C
C
− 4.0
C
− 4.0
− 4.0
− 4.5
− 4.0
− 4.0
− 4.0
− 7.0
OFF
− 4.0
− 4.2
− 4.3
− 4.3
− 4.3
− 0.3
− 4.0
C
(continued)
and not t
11.0
21.0
36.0
18.3
30.5
33.2
28.2
21.0
31.0
Min
6.0
8.5
3.5
1.0
8.2
0.0
7.2
—
—
100 MHz
PC
GZ
equals 4 × T
.
Max
18.0
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-23
for