DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 80

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Host Interface SPI Protocol Timing
3-54
Note: Periodically sampled, not 100% tested
159
160
161
162
163
No.
SS deassertion to HREQ output not
deasserted (CPHA = 0)
SS deassertion pulse width (CPHA = 0)
HREQ in assertion to first SCK edge
HREQ in deassertion to last SCK sampling
edge (HREQ in set-up time) (CPHA = 1)
First SCK edge to HREQ in not asserted
(HREQ in hold time)
SCK (CPOL=0
(Output)
SCK (CPOL = 1
(Output)
(Output)
HREQ
(Input)
(Input)
(Input)
MISO
MOSI
SS
Characteristics
Table 3-21 Serial Host Interface SPI Protocol Timing (continued)
161
148
142
143
Figure 3-34 SPI Master Timing (CPHA = 0)
Valid
MSB
MSB
DSP56362 Technical Data, Rev. 4
152
142
143
Master
Master
Master
Mode
Slave
Slave
163
149
Filter Mode
144
144
Bypassed
Narrow
Wide
148
—
—
—
—
Valid
0.5 × t
LSB
0.5 ×t
0.5 ×t
Expression
141
2.5×T
2.5×T
2.5×T
2.5×T
141
153
T
C
SPICC
SPICC
SPICC
0
0
LSB
+6
C
C
C
C
144
144
+30
+43
+43
+43
+
+
+
149
Freescale Semiconductor
Min
121
174
209
55
16
0
0
100MHz
AA0271
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns