DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 4

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview
1. These ROMs may be factory programmed with data or programs provided by the application developer.
1-4
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•
•
•
On-Chip Memories
— Modified Harvard architecture allows simultaneous access to program and data memories
— 30720 x 24-bit on-chip program ROM
— 6144 x 24-bit on-chip X-data ROM
— 6144 x 24-bit on-chip Y-data ROM
— Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable
— 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)
Off-Chip Memory Expansion
— Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM.
— Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM.
— External memory expansion port( twenty-four data pins for high speed external memory access
— Chip select logic for glueless interface to SRAMs
— On-chip DRAM controller for glueless interface to DRAMs
Peripheral and Support Circuits
— Enhanced serial audio interface (ESAI) includes:
— Serial host interface (SHI) features:
— Byte-wide parallel host interface (HDI08) with DMA support
— DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340,
Instruction
Disabled
Disabled
Enabled
Enabled
– On-Chip Emulation (OnCE‘) module
– Joint Action Test Group (JTAG) test access port (TAP)
– Address trace mode reflects internal program RAM accesses at the external port
allowing for a large number of external accesses per sample)
– Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.
– Master or slave capability
– I
– SPI protocol with multi-master capability
– I
– Ten-word receive FIFO
– Support for 8-, 16-, and 24-bit words.
and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines
Cache
2
2
S, Sony, AC97, and other audio protocol implementations
C protocol with single-master capability
Disabled
Disabled
Enabled
Enabled
Switch
Mode
Program RAM
3072 × 24-bit
2048 × 24-bit
5120 × 24-bit
4096 × 24-bit
DSP56362 Technical Data, Rev. 4
Size
1
1
1
(disabled in 16-bit compatibility mode)
1024 × 24-bit
1024 × 24-bit
Cache Size
Instruction
0
0
X Data RAM Size Y Data RAM Size
5632 × 24-bit
5632 × 24-bit
5632 × 24-bit
5632 × 24-bit
5632 × 24-bit
5632 × 24-bit
3584 × 24-bit
3584 × 24-bit
Freescale Semiconductor