DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 33

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

No
3.9
10 Delay from asynchronous RESET deassertion to first
11 Synchronous reset setup time from RESET
12 Synchronous reset deasserted, delay time from the
13 Mode select setup time
14 Mode select hold time
15 Minimum edge-triggered interrupt request assertion
16 Minimum edge-triggered interrupt request deassertion
17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
Freescale Semiconductor
8
9
Delay from RESET assertion to all pins at reset value
Required RESET duration
external address output (internal reset deassertion)
deassertion to CLKOUT Transition 1
CLKOUT Transition 1 to the first external address
output
width
width
external memory access address out valid
general-purpose transfer output valid caused by first
interrupt instruction execution
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
• Power on, internal oscillator
• During STOP, XTAL disabled (PCTL Bit 16 = 0)
• During STOP, XTAL enabled (PCTL Bit 16 = 1)
• During normal operation
• Minimum
• Maximum
• Minimum
• Maximum
• Minimum
• Maximum
• Caused by first interrupt instruction fetch
• Caused by first interrupt instruction execution
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values
Characteristics
4
DSP56362 Technical Data, Rev. 4
5
3
20.25 T
3.25 × T
3.25 × T
4.25 × T
7.25 × T
20.25 T
Expression
10 × T
75000 × ET
75000 × ET
1000 × ET
50 × ET
2.5 × T
2.5 × T
T
—
C
C
C
C
C
C
C
C
+ 7.50
+ 5.0
+ 7.5
+ 2.0
+ 2.0
+ 2.0
+ 2.0
C
C
C
C
Reset, Stop, Mode Select, and Interrupt Timing
C
C
2
500.0
105.0
10.0
25.0
25.0
34.5
33.5
30.0
44.5
74.5
Min
750
750
5.9
0.0
6.6
6.6
—
—
—
—
100 MHz
211.5
207.5
Max
26.0
10.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
416.7
20.8
20.8
29.1
30.0
37.4
62.4
88.3
Min
625
625
8.3
0.0
5.5
5.5
120 MHz
1
176.2
Max
26.0
—
—
—
—
—
—
Unit
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-7