DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 46

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
3
4
5
6
External Memory Expansion Port (Port A)
3-20
No.
137 CAS assertion pulse width
138 Last CAS deassertion to RAS deassertion
139 CAS deassertion pulse width
140 Column address valid to CAS assertion
141 CAS assertion to column address not valid
142 Last column address valid to RAS deassertion
143 WR deassertion to CAS assertion
144 CAS deassertion to WR assertion
145 CAS assertion to WR deassertion
146 WR assertion pulse widt
147 Last WR assertion to RAS deassertion
148 WR assertion to CAS deassertion
149 Data valid to CAS assertion (Write)
150 CAS assertion to data not valid (write)
151 WR assertion to CAS assertion
152 Last RD assertion to RAS deassertion
153 RD assertion to data valid
154 RD deassertion to data not valid
155 WR assertion to data active
156 WR deassertion to data high impedance
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
read-after-read or write-after-write sequences).
Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state. See
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)
• BRW[1:0] = 00
• BRW[1:0] = 01
• BRW[1:0] = 10
• BRW[1:0] = 11
Characteristics
h
6
DSP56362 Technical Data, Rev. 4
5
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
WCH
t
WCS
CRP
t
CAH
RCS
RCH
RWL
CWL
t
ROH
t
CAS
ASC
RAL
t
t
WP
DH
GA
CP
DS
GZ
3.25 × T
4.25 × T
6.25 × T
0.75 × T
1.75 × T
0.75 × T
0.75 × T
0.25 × T
1.75 × T
1.75 × T
0.25 × T
0.75 × T
0.75 × T
0.5 × T
0.5 × T
0.5 × T
1.5 × T
1.5 × T
Expression
2 × T
0.25 × T
T
T
C
C
− 4.3
− 7.5
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
− 4.0
− 4.0
− 4.0
− 4.2
− 4.5
− 4.0
− 4.0
− 6.0
− 4.0
− 3.8
− 3.7
− 4.3
− 4.3
− 4.0
− 4.0
− 0.3
− 6.0
− 6.0
– 6.0
C
156.5
206.5
306.5
33.5
81.5
21.0
21.0
33.5
96.0
33.7
20.8
70.5
83.2
83.2
33.5
45.7
71.0
37.2
Min
8.8
8.5
0.0
—
—
Figure 3-13
20 MHz
OFF
Max
42.5
12.5
—
—
—
—
—
—
—
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
and not t
1, 2, 3
Freescale Semiconductor
.
102.2
135.5
202.1
21.0
52.3
12.7
12.7
21.0
62.7
21.2
12.5
45.5
54.0
54.0
21.0
29.0
46.0
24.7
Min
4.6
4.3
0.0
—
—
PC
GZ
30 MHz 4
(continued)
.
equals 2 × T
Max
25.8
8.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
for