DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 72

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parallel Host Interface (HDI08) Timing
3.11
3-46
No.
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
Read data strobe assertion width
HACK read assertion width
Read data strobe deassertion width
HACK read deassertion width
Read data strobe deassertion width
reads
HACK deassertion width after “Last Data Register” reads
Write data strobe assertion width
Write data strobe deassertion width
HACK write deassertion width
after ICR, CVR and “Last Data Register” writes
after IVR writes, or
after TXH:TXM writes (with HBE=0), or
after TXL:TXM writes (with HBE=1)
HAS assertion width
HAS deassertion to data strobe assertion
Host data input setup time before write data strobe deassertion
Host data input setup time before HACK write deassertion
Host data input hold time after write data strobe deassertion
Host data input hold time after HACK write deassertion
Read data strobe assertion to output data active from high
impedance
HACK read assertion to output data active from high impedance
Read data strobe assertion to output data valid
HACK read assertion to output data valid
Read data strobe deassertion to output data high impedance
HACK read deassertion to output data high impedance
Output data hold time after read data strobe deassertion
Output data hold time after HACK read deassertion
HCS assertion to read data strobe deassertion
HCS assertion to write data strobe deassertion
HCS assertion to output data valid
Parallel Host Interface (HDI08) Timing
5
,
6
, or between two consecutive CVR, ICR, or ISR reads
4
Characteristics
Table 3-20 Host Interface (HDI08) Timing
8
4
HACK write assertion width
4
4
8
after “Last Data Register”
DSP56362 Technical Data, Rev. 4
3
9
4
5
4
8
4
5, 6
8
4
7
8
2.5 × T
2.5 × T
Expression
T
T
C
C
—
—
—
—
—
—
—
—
—
—
—
—
+ 9.9
+9.9
C
C
+ 6.6
+ 6.6
1, 2
Min
19.9
31.6
13.2
31.6
16.5
19.9
9.9
9.9
0.0
9.9
3.3
3.3
3.3
9.9
—
—
—
100 MHz
Freescale Semiconductor
Max
24.2
19.1
9.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns