DSPB56362AG120 Freescale Semiconductor, DSPB56362AG120 Datasheet - Page 35

• Manufacturer Part Number: DSPB56362AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56362AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (126 kB)
• On-chip Ram: 42kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 120MHz
• Mips: 120
• Device Input Clock Speed: 120MHz
• Ram Size: 42KB
• Program Memory Size: 90KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.46V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Product: DSPs
• Data Bus Width: 24 bit
• Processor Series: DSP563xx
• Core: 56000
• Numeric And Arithmetic Format: Fixed-Point
• Instruction Set Architecture: Modified Harvard
• Device Million Instructions Per Second: 120 MIPS
• Maximum Clock Frequency: 120 MHz
• Program Memory Type: Flash
• Data Ram Size: 42 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Interface Type: SPI, I2C, ESAI, SHI
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
3
4
5
6
7
8
9
No
27 Interrupt Requests Rate
28 DMA Requests Rate
29 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
Freescale Semiconductor
V
Use expression to compute maximum value.
Periodically sampled and not 100% tested.
For an external clock generator, RESET duration is measured during the time in which RESET is asserted, V
EXTAL input is active and valid. For internal oscillator, RESET duration is measured during the time in which RESET is asserted
and V
by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. When
the V
circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize
this state to the shortest possible duration.
If PLL does not lose lock.
When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when
using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
These values depend on the number of wait states (WS) selected.
WS = number of wait states (measured in clock cycles, number of T
This timing depends on several settings: For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and
oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before
executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay. While it is possible to
set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization
delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by
the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The
PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel
with the stop delay counter, and stop recovery will end when the last of these two events occurs. The stop delay counter
completes count or PLL lock procedure completion. PLC value for PLL disable is 0.
The maximum value for ET
(i.e., for 100 MHz it is 4096/100 MHz = 40.96µs). During the stabilization period, T
width may vary, so timing may vary as well.
CC
external memory (DMA source) access address out
valid
• HI08, ESAI, SHI, Timer
• DMA
• IRQ, NMI (edge trigger)
• IRQ, NMI (level trigger)
• Data read from HI08, ESAI, SHI
• Data write to HI08, ESAI, SHI
• Timer
• IRQ, NMI (edge trigger)
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values
= 3.3 V ± 0.16 V; T
CC
CC
is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device
is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both
Characteristics
J
= 0°C to +100°C, C
C
is 4096 (maximum MF) divided by the desired internal frequency
DSP56362 Technical Data, Rev. 4
L
= 50 pF
4.25 × T
Expression
12T
12T
C.
8T
8T
6T
7T
2T
3T
C
C
C
C
C
C
C
C
C
+ 2.0
Reset, Stop, Mode Select, and Interrupt Timing
2
C
, T
44.0
Min
H,
—
—
—
—
—
—
—
—
100 MHz
and T
L
120.0
120.0
will not be constant, and their
Max
80.0
80.0
60.0
70.0
20.0
30.0
—
1
(continued)
37.4
Min
—
—
—
—
—
—
—
—
120 MHz
CC
is valid, and the
100.0
100.0
Max
66.7
66.7
50.0
58.0
16.7
25.0
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-9