EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 138

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–34
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Programmable Duty Cycle
Programmable Phase Shift
The programmable duty cycle allows the PLLs to generate clock outputs with a
variable duty cycle. This feature is supported on the PLL post-scale counters. The
duty-cycle setting is achieved by a low and high time-count setting for the post-scale
counters. The Quartus II software uses the frequency input and the required multiply
or divide rate to determine the duty cycle choices. The post-scale counter value
determines the precision of the duty cycle. The precision is defined by 50% divided by
the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are
possible for duty-cycle choices between 5% to 90%.
Combining the programmable duty cycle with programmable phase shift allows the
generation of precise non-overlapping clocks.
For Arria II GZ devices, if the PLL is in external feedback mode, set the duty cycle for
the counter driving the fbin pin to 50%.
Use phase shift to implement a robust solution for clock delays in Arria II devices.
Implement phase shift with a combination of the VCO phase output and the counter
starting time. A combination of the VCO phase output and counter starting time is the
most accurate method of inserting delays because it is purely based on counter
settings, which are independent of process, voltage, and temperature (PVT).
You can phase-shift the output clocks from the Arria II PLLs in either of these two
resolutions:
■
■
Fine-resolution phase shifts are implemented by allowing any of the output counters
(C[n..0]) or the m counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution. The minimum
delay time that you can insert with this method is defined in
Equation 5–1. Fine-Resolution Phase Shifts for Arria II Devices
where f
For example, if f
equals 156.25 ps. The PLL operating frequency, which is governed by the reference
clock frequency and the counter settings, defines this phase shift.
Fine resolution with VCO phase taps
Coarse resolution with counter starting time
R EF
is the input reference clock frequency.
REF
is 100 MHz, n is 1, and m is 8, then f
Φ
fine
=
1
8
T
VCO
=
8f
Chapter 5: Clock Networks and PLLs in Arria II Devices
VCO
1
=
8Mf
N
REF
VCO
is 800 MHz and
December 2010 Altera Corporation
Equation
PLLs in Arria II Devices
5–1.
Φ
fin e