EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 442

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Arria II Device Handbook Volume 2: Transceivers
Deterministic Latency
1
1
1
This mode is typically used to create a CPRI or Open Base Station Architecture
Initiative Reference Point 3 (OBSAI RP3) interface to connect radio frequency (RF)
processing remote radio heads located at the top of cell phone towers with the base
band processing equipment typically found at the bottom of cell phone towers.
CPRI and OBSAI protocols have a requirement for the accuracy of the round trip
delay measurement for single-hop and multi-hop connections to be within
± 16.276 ns. For single hops, the round trip delay may only vary within ± 16.276 ns.
For multi-hop connections, the round trip variation is equal to ± 16.276 ns divided by
the number of hops.
Deterministic latency is the only functional mode that allows 16-bit and 20-bit data on
the PCS-to-PMA interface. This is to allow data rates of 2457.6, 3072, 4915.2, and
6144 Mbps for the CPRI protocol and to allow 3072 and 6144 Mbps data rates for the
OBSAI protocol.
When you choose the deterministic latency protocol in the ALTGX MegaWizard
Plug-In Manager, the bit-slip circuitry in the transmitter channel is automatically
enabled and the RX phase compensation FIFO is automatically set to register mode. In
addition, two extra ports are created—the rx_bitslipboundaryselectout output port
from the receiver ’s word aligner and the tx_bitslipboundaryselect input port for
the transceiver bit-slip circuitry. You can also set the TX phase compensation FIFO in
register mode.
In register mode, the phase compensation FIFO acts as a register and removes the
uncertainty in latency. To ensure that the phase relationship between the low-speed
parallel clock and the CMU PLL input reference clock is deterministic, you can enable
the CMU PLL feedback path, which is only available in this mode. When the feedback
path is enabled, you must provide an input reference clock to the CMU PLL that has
the same frequency as the low-speed parallel clock.
The information on the rx_bitslipboundaryselectout[4:0] output port helps
calculate the latency through the receiver datapath. Connect
rx_bitslipboundaryselectout[4:0] to tx_bitslipboundaryselect[4:0] to cancel
out the latency uncertainty.
The number of bits slipped in the receiver’s word aligner is shown on the
rx_bitslipboundaryselectout[4:0] output port. In 8- or 10-bit channel width, the
number of bits slipped in the receiver path is given out sequentially on this output.
For example, if zero bits are slipped, the output on
rx_bitslipboundaryselectout[4:0] shows a value of 0(5'b00000); if two bits are
slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 2
(5'b00010). In 16- or 20-bit channel width, the output is 19 minus the number of bits
slipped. For example, if zero bits are slipped, the output on
rx_bitslipboundaryselectout[4:0] shows a value of 19 (5'b10011); if two bits are
slipped, the output on rx_bitslipboundaryselectout[4:0] shows a value of 17
(5'b10001).
You can slip zero to nine bits with 8- or 10-bit channel width and you can slip zero to
19 bits with 16- or 20-bit channel width.
Chapter 1: Transceiver Architecture in Arria II Devices
December 2010 Altera Corporation
Functional Modes