EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 177
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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Chapter 6: I/O Features in Arria II Devices
OCT Support
OCT Support
December 2010 Altera Corporation
Arria II devices feature OCT to provide I/O impedance matching and termination
capabilities. OCT maintains signal quality, saves board space, and reduces external
component costs.
Arria II devices support the following features:
■
■
■
■
■
■
■
Arria II devices support OCT in all user I/O banks by selecting one of the OCT I/O
standards. Arria II devices support OCT in the same I/O bank with different I/O
standards if they use the same VCCIO supply voltage. You can independently
configure each I/O buffer in an I/O bank to support OCT or programmable current
strength. However, you cannot configure both R
strength for the same I/O buffer.
A pair of RUP and RDN pins are available in a given I/O bank for Arria II GX
series-calibrated termination and shared for Arria II GZ series- and parallel-calibrated
termination. RUP and RDN pins share the same V
I/O bank where they are located. RUP and RDN pins are dual-purpose I/Os, and
function as regular I/Os if you do not use the calibration circuit.
For R
■
■
For R
■
■
R
Arria II devices support driver-impedance matching to provide the I/O driver with
controlled output impedance that closely matches the impedance of the transmission
line. As a result, you can significantly reduce reflections. Arria II devices support
R
S
S
OCT for single-ended I/O standards.
OCT without Calibration for Arria II Devices
“R
“R
“Left-Shift R
“Expanded R
“R
“R
“Dynamic R
The RUP pin is connected to V
resistor for an on-chip series termination value of 25- Ω or 50- Ω , respectively.
The RDN pin is connected to GND through an external 25- Ω ±1% or 50- Ω ±1%
resistor for an R
The RUP pin is connected to V
The RDN pin is connected to GND through an external 50- Ω ±1% resistor.
S
T
S
S
D
T
OCT, the connections are as follows:
OCT, the connections are as follows:
OCT without Calibration for Arria II Devices”
OCT with Calibration for Arria II Devices”
OCT with Calibration for Arria II GZ Devices”
OCT for Arria II LVDS Input I/O Standard”
S
S
S
and R
OCT Control for Arria II GZ Devices”
OCT with Calibration for Arria II GZ Devices”
S
OCT value of 25- Ω or 50- Ω , respectively.
T
OCT for Single-Ended I/O Standard for Arria II GZ Devices”
CCIO
CCIO
Arria II Device Handbook Volume 1: Device Interfaces and Integration
through an external 25- Ω ±1% or 50- Ω ±1%
through an external 50- Ω ±1% resistor.
CCIO
S
OCT and programmable current
and GND, respectively, with the
6–19
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