EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 53
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45DF29I5N PDF datasheet #6
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Chapter 3: Memory Blocks in Arria II Devices
Memory Features
Figure 3–5. Address Clock Enable During Write Cycle Waveform for M9K and M144K Blocks
Figure 3–6. Address Clock Enable During Write Cycle Waveform for MLABs
December 2010 Altera Corporation
latched address
(inside memory)
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
addressstall
addressstall
wraddress
wraddress
Figure 3–5
M144K blocks.
Figure 3–6
MLABs.
inclock
inclock
wren
wren
data
data
an
an
shows the address clock enable waveform during write cycle for M9K and
XX
shows the address clock enable waveform during the write cycle for
XX
a0
a0
00
00
XX
a0
XX
a0
a1
01
a1
01
XX
01
XX
01
02
a2
02
a2
XX
XX
a1
Arria II Device Handbook Volume 1: Device Interfaces and Integration
XX
XX
a1
XX
XX
02
02
a3
03
a3
03
00
00
a4
04
a4
04
a4
a4
03
03
a5
05
a5
05
04
04
a5
a5
05
05
a6
a6
06
06
3–7
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