EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 315

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
JTAG Configuration
Table 9–14. Dedicated Configuration Pin Connections During JTAG Configuration (Part 1 of 2)
December 2010 Altera Corporation
nCE
nCEO
MSEL
nCONFIG
Signal
On all Arria II devices in the chain, nCE must be driven low by connecting it to GND ground, pulling it low
using a resistor, or driving it by some control circuitry. For devices that are also in multi-device FPP, AS, or
PS configuration chains, the nCE pins must be connected to GND during JTAG configuration or JTAG
must be configured in the same order as the configuration chain.
On all Arria II devices in the chain, you can leave nCEO floating or connected to nCE of the next device.
Do not leave these pins floating. These pins support whichever non-JTAG configuration is used in
production. If you only use JTAG configuration, tie these pins to GND.
Driven high by connecting to V
circuitry.
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration after completion. At
the end of configuration, the software checks the state of CONF_DONE through the JTAG
port. When the Quartus II software generates a Jam
chain, it contains instructions so that all the devices in the chain are initialized at the
same time. If CONF_DONE is not high, the Quartus II software indicates that
configuration has failed. If CONF_DONE is high, the software indicates that
configuration was successful. After the configuration bitstream is transmitted serially
using the JTAG TDI port, the TCK port is clocked an additional 1,094 cycles to perform
device initialization.
Arria II devices have dedicated JTAG pins that always function as JTAG pins. Not
only can you perform JTAG testing on Arria II devices before and after, but also
during configuration. While other device families do not support JTAG testing during
configuration, Arria II devices support the bypass, ID code, and sample instructions
during configuration without interrupting configuration. All other JTAG instructions
may only be issued by first interrupting configuration and reprogramming I/O pins
using the CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured using the JTAG port
and when issued, interrupts configuration. This instruction allows you to perform
board-level testing prior to configuring the Arria II device or waiting for a
configuration device to complete configuration. After configuration is interrupted
and JTAG testing is complete, you must reconfigure the part using JTAG
(PULSE_CONFIG instruction) or by pulsing nCONFIG low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Arria II
devices do not affect JTAG boundary-scan or programming operations. Toggling
these pins does not affect JTAG operations (other than the usual boundary-scan
operation).
When designing a board for JTAG configuration of Arria II devices, consider the
dedicated configuration pins.
JTAG configuration.
CCIO
or V
CCPGM
Table 9–14
, pulling up using a resistor, or driven high by some control
Description
Arria II Device Handbook Volume 1: Device Interfaces and Integration
lists how these pins are connected during
TM
file (.jam) for a multi-device
9–35