EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 251

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
Differential Receiver
Figure 8–8. LVDS Receiver Block Diagram
Notes to
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(2) The rx_out port has a maximum data width of 10 bits.
(3) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
December 2010 Altera Corporation
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
8–8:
10
You can statically assign the V
the assignment name for programmable V
software Assignment Editor.
Table 8–6. Programmable V
The Arria II device family has a dedicated circuitry to receive high-speed differential
signals in side or row I/Os.
receiver. The receiver has a differential buffer and PLLs that can be shared between
the transmitter and receiver, a DPA block, a synchronizer, a data realignment block,
and a deserializer. The differential buffer can receive LVDS, mini-LVDS, and RSDS
signal levels, which are statically set in the Quartus II software Assignment Editor.
Figure 8–8
Programmable Differential Output
Voltage (V
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Assignment Name
Deserializer
DOUT DIN
OD
shows a block diagram of an LVDS receiver in the right I/O bank.
)
IOE
2
(Note
PLL (3)
3
1),
Multiplexer
DOUT DIN
Bit Slip
Clock
OD
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
Settings in Quartus II Software Assignment Editor
(2)
Figure 8–8
diffioclk
OD
settings from the Assignment Editor.
rx_inclock
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Arria II GX Device
shows the hardware blocks of the Arria II
OD
8 Serial LVDS
Clock Phases
and its possible values in the Quartus II
2
Synchronizer
DOUT DIN
Assignment Value
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
DPA Circuitry
Retimed
DPA Clock
Arria II GZ Device
Data
0, 1, 2, 3
Table 8–6
DIN
LVDS Clock Domain
DPA Clock Domain
+
lists
rx_in
8–11