EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 495

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
CMU PLL and Receiver CDR Input Reference Clocking
Figure 2–4. Inter-Transceiver Block Clock Lines
Note to
(1) This figure shows the ITB clock lines on the left side of the EP2AGX60FF35 device. The number of ITB clock lines available in any Arria II GX or
December 2010 Altera Corporation
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
GZ device is equal to the number of refclk pins available in that device.
Figure
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Four RX CDRs
Four RX CDRs
Four RX CDRs
Four RX CDRs
and
and
and
and
2–4:
Inter-Transceiver Block Clock Lines
The ITB clock lines provide an input reference clock path from the refclk pins of one
transceiver block to the CMU PLLs and receiver CDRs of other transceiver blocks. In
designs that have channels located in different transceiver blocks, the ITB clock lines
eliminate the need to connect the on-board reference clock crystal oscillator to the
refclk pin of each transceiver block. The ITB clock lines also drive the clock signal on
the refclk pins to the clock logic in the FPGA fabric.
Each refclk pin drives one ITB clock line for a total of up to eight ITB clock lines on
the left side of the device, as shown in
6
6
6
6
(Note 1)
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
Figure
2–4.
/2
/2
/2
/2
/2
/2
/2
/2
Arria II Device Handbook Volume 2: Transceivers
refclk1
refclk1
refclk1
refclk1
refclk0
refclk0
refclk0
refclk0
ITB[7:0]
To FPGA Fabric
2–5