EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 101
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Design Considerations
Read During Write
Figure 4–18. Stratix III Read-During-Write Data Flow
© May 2009 Altera Corporation
You can customize the read-during-write behavior of the Stratix III TriMatrix memory
blocks to suit your design needs. Two types of read-during-write operations are
available: same port and mixed port.
two types.
Same-Port Read-During-Write Mode
This mode applies to either a single-port RAM or the same port of a true dual-port
RAM. In same-port read-during-write mode, three output choices are available: new
data mode (or flow-through), old data mode, or don’t care mode. In new data mode,
the new data is available on the rising edge of the same clock cycle on which it was
written. In old data mode, the RAM outputs reflect the old data at that address before
the write operation proceeds. In don’t care mode, the RAM outputs don’t care values
for a read-during-write operation.
If you are not using the new data mode or old data mode, you should select the don’t
care mode. Using the don’t care mode increases the flexibility in the type of memory
block used, provided you do not assign block type when instantiating a memory
block. You may also get potential performance gain by selecting the don’t care mode.
Port A
data in
Port A
data out
Figure 4–18
Port B
data in
Port B
data out
shows the difference between the
Stratix III Device Handbook, Volume 1
Mixed-port
data flow
Same-port
data flow
4–21
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