EP3SL150F1152C2N Altera, EP3SL150F1152C2N Datasheet - Page 145
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C2N
Manufacturer Part Number
EP3SL150F1152C2N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2409
EP3SL150F1152C2NES
EP3SL150F1152C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3SL150F1152C2N
Manufacturer:
ALTERA
Quantity:
20 000
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Chapter 5: DSP Blocks in Stratix III Devices
Application Examples
© March 2010 Altera Corporation
When you use both the input cascade and chainout features, the DSP block uses an
18-bit delay register in the boundary of each half-DSP block or from block-to-block to
synchronize the input scan chain data with the chainout data. The top half computes
the sum of product and chains the output to the next block after the output register.
The output register uses the delay register to delay the cascade input by one clock
cycle to compensate the latency for the bottom half.
For applications in which the system clock is slower than the speed of the DSP block,
the multipliers can be time-multiplexed to improve efficiency. This makes
multi-channel and semi-parallel FIR structures possible. The structure to achieve this
is similar to
chain is no longer used and each half-DSP block is used in Four-Multiplier Mode with
independent inputs.
In most cases, only the final stage FIR tap with the rounding and saturation unit is
deployed.
Figure 5–22
Figure 5–24
and
Figure
shows an example for chained cascaded summation.
5–23. The main difference is that the input cascade
Stratix III Device Handbook, Volume 1
5–39
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